Elsevier

Current Applied Physics

Volume 20, Issue 12, December 2020, Pages 1314-1320
Current Applied Physics

Local mismatch and noise investigation for pre and post multilayer pHEMTs

https://doi.org/10.1016/j.cap.2020.09.006Get rights and content

Highlights

  • Study of local mismatch of pre and post multilayer structure.

  • The threshold voltage, built in potential and the net doping concentration of the 2-DEG estimation.

  • The underlying electrical parameter of the transistors as well as the RF figure of merit.

  • The noise parameters such as minimum noise figure, associate gain, noise resistance, magnitude of the optimum reflection.

  • Slight performance variability between different devices is attributed to centre-to-edge mismatch.

Abstract

The key objective of this study is to investigate the local mismatch of pre and post multilayer structure on the active devices. Five pre and post multilayer structure pHEMTs on the same wafer within the same cell between adjacent devices are considered. As the study of local mismatch ensures good yields and a way to gain insights about the technology various comparisons are made including the effects of multilayer structuring. The threshold voltage, built-in potential and the net doping concentration of the 2-DEG of the devices are extracted through capacitance-voltage data. The underlying electrical parameter of the transistors as well as the RF figure of merit has been analyzed. The microwave noise related parameters namely minimum noise figure, associate gain, noise resistance, magnitude of the optimum reflection are also discussed and investigated. Centre-to-edge mismatch results in minor variation in performance between devices. These studies would help within the advancement of solid, proficient and low cost generation of future compact structure in 3-D multilayer MMICs.

Introduction

The growth of the wireless communications and sensors market has led to recent interest in highly integrated MMICs for wireless applications with a millimeter wave range. Later improvement of multilayer coplanar waveguide (CPW) MMIC innovation guarantees realization of 3D MMIC in which expansive area-occupying passive components are translated from horizontal into vertical arrangement coming about compact structure [[1], [2], [3]]. The other primary points of interest of this innovation are disposal of via-holes and wafer-thinning giving elective execution arrangement separated from the conventional MMICs [4]. By doing this sort of arrangement, significant chip size reduction can be observed and this will allow more devices to be fabricated on a single chip [5,6]. The probing pads have also been fabricated on both the pre-multilayer processed (virgin) and post-multilayer-processed (multilayer) pHEMTs. The layout designs of the probing pads of virgin and multilayer pHEMTs are different due to some constraints of initial multilayer processing. Nonetheless, only the parasitic of the interconnects are expected to be affected, the active region of the devices is considered to be the same as the pHEMTs incorporated in multilayer CPW MMIC technology will have layers of polyimide and metal layers added on top of the pHEMTs [[7], [8], [9]]. It has been so for several years; the semiconductor industry gained a lot of attention for MMIC fabrication. So, the local mismatch study is an important issue before and after 3-D integration. Some previous uniformity or mismatch study on pre and post multilayer processed pHEMTs based on small signal modelling and DC behaviour are reported [10,11]. All these existing uniformity studies were based on a device taken from each cell form different parts of the wafer. So, it is necessary to investigate the local mismatch i.e., on the same wafer within the same cell between adjacent devices of pre and post multilayer structure pHEMTs. This paper analyzes the local mismatch on the performance of pHEMTs before and after 3-D multilayer MMIC process. Five pre and post multilayer processed devices from the same cell are measured to observe the variation in their performance by means capacitance-voltage, DC and RF, and microwave noise data. As an example, the mismatch between the post multilayer processed devices in output current before threshold voltage is around 2.23% except for the centre device. But the same mismatch after threshold voltage falls significantly below 2%. The overall uniformity is found to be generally good except the specific cells are positioned near to the edge or centre of the wafer exhibits a bit lower output current, transconductance, gain, cut-off frequency and maximum frequency and higher noise. This is found to be true for both pre and post multilayer processed cases. After multilayer process, the minimum noise figure, NFmin is found to be slightly higher in magnitude. This is due to the higher parasitic resistance resulting from the bigger physical dimensions of interconnects and probing pads. This work presents unique results on characterisation of the local mismatch of the devices which is necessary to ensure adequate circuit design depending on the application of interest.

Section snippets

Fabrication and experimental techniques

There are seven steps involved in multilayer 3-D MMIC fabrication process such as opening Si3N4 window using buffered HF to access the pre-fabricated (virgin) pHEMT (see. Fig. 1). The next steps are deposition of Ni–Cr resistor, metal 1 (Ti/Au) layer, polyimide 1 layer, metal 2 (Ti/Au) layer, polyimide 1 layer and metal 3 (Ti/Au) layer, respectively. In realization of multilayer structures utilising this technology, a few preparing perspectives have been examined counting polyimide spin,

Results and analysis

In this section an attempt to understand the mismatch (e.g.; uniformity of adjacent devices) in pHEMTs are studied. Mismatch is defined as the differential performance of two or more devices in a single integrated circuit [17]. Such a study is very important when high precision analogue circuits have to be designed. In this work, only the local mismatch (on the same wafer and within the same cell) between adjacent devices is considered. The cells (1,1) for virgin and (2,2) for multilayer are

Conclusions

The investigation of local mismatch on active devices is successfully accomplished. Various comparisons between the pre and post-processed multilayer structure pHEMTs are made to study these effects on device performance. It is found that the multilayer MMIC structure raised no significant statistical impact on the capacitance-voltage, current-voltage and gain and noise characteristics of the pHEMTs. This data certainly will provide a brief insight into the minute variations of parameters

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgment

The authors would like to acknowledge “University of Chittagong, Bangladesh, research grant (2018–2019)” for their partial financial support in this work.

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