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CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency

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Abstract

This paper presents a novel IEEE 802.16e (WiMAX) based decoder that performs close to the 5G code but without the expensive hardware re-development cost. The design uses an extension of the existing WiMAX parity check code to reduce the initial decoding latency and power consumption while keeping the decoder throughput at maximum. It achieves similar Frame Error Rate (FER) compared to 5G (0.1 dB off), and most notably the error curves trend down like 5G instead flooring. At FER= 10−3 there is 0.1 dB gain in the FER code performance compared to WiMAX. An implementation of the design is a modified version of the existing fully-parallel WiMAX decoder that supports multi-rate codeword size and reduces the initial latency by 33%. Additionally, for SNR greater than 3 dB, decoding only the shorter code reduces the power consumption by 34%.

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References

  1. Gallager, R. (1962). Low-density parity-check codes. IRE Transactions on Information Theory, 8(1), 21–28.

    Article  MathSciNet  Google Scholar 

  2. MacKay, D. J., & Neal, R. M. (1996). Near Shannon limit performance of low density parity check codes. Electronics Letters, 32(18), 1645–1646.

    Article  Google Scholar 

  3. Maiya, S. V., Costello, D. J., & Fuja, T. E. (2012). Low latency coding: Convolutional codes vs. LDPC codes. IEEE Transactions on Communications, 60(5), 1215–1225.

    Article  Google Scholar 

  4. Battaglioni, M., Tasdighi, A., Baldi, M., Tadayon, M. H., & Chiaraluce, F. (2018) Compact QC-LDPC block and SC-LDPC convolutional codes for low-latency communications. In 2018 IEEE 29th Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC) (pp. 1-5). Bologna: IEEE.

  5. Sham, C.-W., Chen, X., Lau, F. C. M., Zhao, Y., & Tam, W. M. (2013). A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(7), 1857–1869.

    Article  MathSciNet  Google Scholar 

  6. Cain, J., Clark, G., & Geist, J. (1979). Punctured convolutional codes of rate (n-1)/n and simplified maximum likelihood decoding (Corresp.). IEEE Transactions on Information Theory, 25(1), 97–100.

    Article  MathSciNet  Google Scholar 

  7. Hagenauer, J. (1988). Rate-compatible punctured convolutional codes (RCPC codes) and their applications. IEEE Transactions on Communications, 36(4), 389–400.

    Article  Google Scholar 

  8. Yasuda, Y., Kashiki, K., & Hirata, Y. (1984). High-rate punctured convolutional codes for soft decision Viterbi decoding. IEEE Transactions on Communications, 32(3), 315–319.

    Article  Google Scholar 

  9. Li, J., & Narayanan, K. R. (2002). Rate-compatible Low Density Parity Check Codes for Capacity-approaching ARQ Schemes in Packet Data Communications. In Communications, Internet, and Information Technology (pp. 201-206).

  10. Van Nguyen, T., Nosratinia, A., & Divsalar, D. (2012). The design of rate-compatible protograph LDPC codes. IEEE Transactions on Communications, 60(10), 2841–2850.

    Article  Google Scholar 

  11. Lin, S., & Yu, P. (1982). A hybrid ARQ scheme with parity retransmission for error control of satellite channels. IEEE Transactions on Communications, 30(7), 1701–1719.

    Article  Google Scholar 

  12. Liu, J., & de Lamare, R. C. (2015). Rate-compatible LDPC codes with short block lengths based on puncturing and extension techniques. AEU-International Journal of Electronics and Communications, 69(11), 1582–1589.

    Article  Google Scholar 

  13. Document 3GPP R1-1711982 3GPP TSG RAN WG1 Meeting AH NR2, 3GPP (2017). https://www.3gpp.org. Accessed Mar 2019.

  14. Report ITU-R M.2410-0. (2017). Minimum requirements related to technical performance for IMT-2020 radio interface(s).

  15. Hu, X.-Y., Eleftheriou, E., Arnold, D.-M., & Dholakia, A. (2001). Efficient implementations of the sum-product algorithm for decoding LDPC codes. In GLOBECOM’01. IEEE Global Telecommunications Conference (Cat. No. 01CH37270) (Vol. 2, pp. 1036-1036E vol. 1032). San Antonio, TX: IEEE.

  16. Chen, J., & Fossorier, M. P. (2002). Density evolution for two improved BP-based decoding algorithms of LDPC codes. IEEE Communications Letters, 6(5), 208–210.

    Article  Google Scholar 

  17. Blanksby, A. J., & Howland, C. J. (2002). A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder. IEEE Journal of Solid-State Circuits, 37(3), 404–412.

    Article  Google Scholar 

  18. Yeo, E., Nikolic, B., & Anantharam, V. (2002). Architectures and implementations of low-density parity check decoding algorithms. In The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002 (Vol. 3, pp. III-III), Tulsa, OK: IEEE.

  19. Zhang, T., & Parhi, K. K. (2002). A 54 mbps (3, 6)-regular FPGA LDPC decoder. In IEEE workshop on signal processing systems (pp. 127-132). San Diego, CA: IEEE.

  20. Hocevar, D. E. (2004). A reduced complexity decoder architecture via layered decoding of LDPC codes. In IEEE Workshop on Signal Processing Systems, 2004. SIPS 2004 (pp. 107-112). Austin, TX: IEEE.

  21. Liu, G. (2016). Gaussian noise generator IP Core specification. Available from: https://github.com/liuguangxi/gng. Accessed Mar 2019.

  22. Chandrasetty, V. A., & Aziz, S. M. (2012). An area efficient LDPC decoder using a reduced complexity min-sum algorithm. Integration, 45(2), 141–148.

    Article  Google Scholar 

  23. Patel, D. J., & Engineer, P. (2017). Design and implementation of quasi cyclic low density parity check (QC-LDPC) code on FPGA. In 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) (pp. 181-185). Chennai: IEEE.

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Correspondence to Sina Pourjabar.

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Pourjabar, S., Choi, G.S. CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency. J Sign Process Syst 93, 855–862 (2021). https://doi.org/10.1007/s11265-020-01597-0

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  • DOI: https://doi.org/10.1007/s11265-020-01597-0

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