Abstract
The current method of designing robust digital circuits requires running analysis and simulations over multiple process-voltage-temperature (PVT) points to meet the design specifications. However, in small-delay defect (SDD) testing, the computation of the SDD test quality uses a single PVT point. This makes it less accurate to describe the test quality for chips that operate under a different point. In this paper we explore the idea of calculating the SDD quality metric over multiple PVT points using multiple SDD test quality metrics including our previously proposed metric, the weighted slack percentage (WeSPer). The results are obtained by running extensive simulations with a CMOS 28nm technology and calculating the different SDD test quality metrics under 54 different PVT points, 3 test speeds and 2 different types of test patterns for 14 benchmark circuits. The results are then analyzed and compared with respect to the test-escape window size. The comparison shows that WeSPer is the most responsive SDD test quality metric to the change in the test-escape window size. Since the simulation of 54 PVT points and the delay information extraction can be lengthy, this paper also shows two methods of estimating WeSPer across all PVT points by either predicting the results using only 3 PVT points or by considering the worst case scenario.
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Acknowledgments
The authors would like to thank CMC Microsystems and CMP for providing the CAD tools and access to a 28nm PDK, Octasic for providing partial financial support and scientific guidance, and the Natural Science and Engineering Research Council for providing partial funding.
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Al-Terkawi Hasib, O., Savaria, Y. & Thibeault, C. Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. J Electron Test 35, 823–838 (2019). https://doi.org/10.1007/s10836-019-05832-w
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DOI: https://doi.org/10.1007/s10836-019-05832-w