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Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics

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Abstract

The current method of designing robust digital circuits requires running analysis and simulations over multiple process-voltage-temperature (PVT) points to meet the design specifications. However, in small-delay defect (SDD) testing, the computation of the SDD test quality uses a single PVT point. This makes it less accurate to describe the test quality for chips that operate under a different point. In this paper we explore the idea of calculating the SDD quality metric over multiple PVT points using multiple SDD test quality metrics including our previously proposed metric, the weighted slack percentage (WeSPer). The results are obtained by running extensive simulations with a CMOS 28nm technology and calculating the different SDD test quality metrics under 54 different PVT points, 3 test speeds and 2 different types of test patterns for 14 benchmark circuits. The results are then analyzed and compared with respect to the test-escape window size. The comparison shows that WeSPer is the most responsive SDD test quality metric to the change in the test-escape window size. Since the simulation of 54 PVT points and the delay information extraction can be lengthy, this paper also shows two methods of estimating WeSPer across all PVT points by either predicting the results using only 3 PVT points or by considering the worst case scenario.

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References

  1. Ahmed N, Tehranipoor M (2009) A novel faster-than-at-speed transition-delay test method considering ir-drop effects. IEEE Trans Comput-Aid Des Integ Circuit Syst 28(10):1573–1582. https://doi.org/10.1109/TCAD.2009.2028679

    Article  Google Scholar 

  2. Ahmed N, Tehranipoor M, Jayaram V (2006) Timing-based delay test for screening small delay defects. In: Proceedings of the 43rd annual Design Automation Conference, ACM, pp 320–325

  3. Bao F, Peng K, Tehranipoor M, Chakrabarty K (2013) Generation of effective 1-Detect TDF patterns for detecting small-delay defects. IEEE Trans Comput-Aided Design Integr Circuits Syst 32(10):1583–1594. https://doi.org/10.1109/TCAD.2013.2266374

    Article  Google Scholar 

  4. Bao F, Tehranippor M, Chen H (2013) Worst-case critical-path delay analysis considering power-supply noise. In: Proceedings of the 22nd asian test symposium (ATS), 2013. https://doi.org/10.1109/ATS.2013.17, pp 37–42

  5. Bushnell M, Agrawal V (2005) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits (Frontiers in Electronic Testing). Springer, New York

    Google Scholar 

  6. Chakravarty S, Devta-Prasanna N, Gunda A, Ma J, Yang F, Guo H, Lai R, Li D (2012) Silicon evaluation of faster than at-speed transition delay tests. In: Proceedings of 2012 IEEE 30th VLSI Test Symposium (VTS). https://doi.org/10.1109/VTS.2012.6231084, pp 80–85

  7. Chang CY, Liao KY, Hsu SC, Li J, Rau JC (2013) Compact test pattern selection for small delay defect. IEEE Trans Comput-Aided Design Integr Circuits Syst 32(6):971–975. https://doi.org/10.1109/TCAD.2013.2237946

    Article  Google Scholar 

  8. Cheng KT, Chen HC (1996) Classification and identification of nonrobust untestable path delay faults. IEEE Trans Comput-Aided Design Integr Circuits Syst 15(8):845–853. https://doi.org/10.1109/43.511566

    Article  Google Scholar 

  9. Dasdan A, Hom I (2006) Handling inverted temperature dependence in static timing analysis. ACM Trans Des Autom Electron Syst 11(2):306–324. https://doi.org/10.1145/1142155.1142158

    Article  Google Scholar 

  10. Devta-Prasanna N, Goel S, Gunda A, Ward M, Krishnamurthy P (2009) Accurate measurement of small delay defect coverage of test patterns. In: 2009 Proceedings of international test conference. https://doi.org/10.1109/TEST.2009.5355644, pp 1–10

  11. Fu X, Li H, Li X (2012) Testable path selection and grouping for faster than at-speed testing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (2):236–247. https://doi.org/10.1109/TVLSI.2010.2099243

    Article  Google Scholar 

  12. Goel SK, Devta-Prasanna N, Turakhia RP (2009) Effective and efficient test pattern generation for small delay defect. In: 2009 Proceedings of the IEEE 27th VLSI Test Symposium, IEEE, pp 111–116

  13. Graphics M (2018) The tessent product suit

  14. Gupta P, Hsiao MS (2004) Alaptf: a new transition fault model and the atpg algorithm. In: 2004 Proceedings of the International Test Conference, IEEE, pp 1053–1060

  15. Hasib OAT, Savaria Y, Thibeault C (2016) Wesper: a flexible small delay defect quality metric. In: Proceedings of the IEEE 34th VLSI Test Symposium (VTS). https://doi.org/10.1109/VTS.2016.7477266, pp 1–6

  16. Ikeda M, Ishii K, Sogabe T, Asada K (2007) Datapath delay distributions for data/instruction against pvt variations in 90nm cmos. In: 2007 Proceedings of the 14th IEEE International Conference on Electronics, Circuits and Systems. https://doi.org/10.1109/ICECS.2007.4510953, pp 154–157

  17. Iyengar V, Rosen BK, Spillinger I (1988) Delay test generation. i. concepts and coverage metrics. In: 1988 International Test Conference on proceedings of the New frontiers in testing. https://doi.org/10.1109/TEST.1988.207873, pp 857–866

  18. Kampmann M, Hellebrand S (2017) Design-for-fast: supporting x-tolerant compaction during faster-than-at-speed test. In: 2017 Proceedings of IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS). https://doi.org/10.1109/DDECS.2017.7934564, pp 35–41

  19. Kruseman B, Majhi A, Gronthoud G, Eichenberger S (2004) On hazard-free patterns for fine-delay fault testing. In: 2004 Proceedings of the international test conference. https://doi.org/10.1109/TEST.2004.1386955, pp 213–222

  20. Lin X, Tsai KH, Wang C, Kassab M, Rajski J, Kobayashi T, Klingenberg R, Sato Y, Hamada S, Aikyo T (2006) Timing-aware ATPG for high quality at-speed testing of small delay defects. In: 2006 Proceedings of the 15th asain test symposium. https://doi.org/10.1109/ATS.2006.261012, pp 139–146

  21. Mahmod J, Millican S, Guin U, Agrawal V (2019) Special session: Delay fault testing - present and future. In: Proceedings of IEEE 37th VLSI Test Symposium (VTS). https://doi.org/10.1109/VTS.2019.8758662, pp 1–10

  22. Mitra S, Volkerink E, McCluskey EJ, Eichenberger S (2004) Delay defect screening using process monitor structures. In: Proceedings of IEEE 22nd VLSI test symposium (VTS). IEEE Computer Society, pp 43–43

  23. Mohammad TKC, Ke P (2011) Test and diagnosis for small-delay defects. Springer, New York

    Google Scholar 

  24. Park ES, Mercer M, Williams T (1992) The total delay fault model and statistical delay fault coverage. IEEE Trans Comput 41(6):688–698. https://doi.org/10.1109/12.144621

    Article  Google Scholar 

  25. Pei S, Geng Y, Li H, Liu J, Jin S (2015) Enhanced lccg: a novel test clock generation scheme for faster-than-at-speed delay testing. In: Proceedings of the 20th Asia and South Pacific Design Automation Conference. https://doi.org/10.1109/ASPDAC.2015.7059058, pp 514–519

  26. Pei S, Li H, Jin S, Liu J, Li X (2015) An on-chip frequency programmable test clock generation and application method for small delay defect detection 49:87–97. https://doi.org/10.1016/j.vlsi.2014.12.003

    Article  Google Scholar 

  27. Peng K, Thibodeau J, Yilmaz M, Chakrabarty K, Tehranipoor M (2010) A novel hybrid method for sdd pattern grading and selection. In: 2010 Proceedings of the 28th VLSI Test Symposium (VTS). https://doi.org/10.1109/VTS.2010.5469619, pp 45–50

  28. Peng K, Yilmaz M, Tehranipoor M, Chakrabarty K (2010) High-quality pattern selection for screening small-delay defects considering process variations and crosstalk. In: Proceedings of the design, automation & test in europe conference & exhibition (DATE). https://doi.org/10.1109/DATE.2010.5457036, vol 2010, pp 1426–1431

  29. Peng K, Yilmaz M, Chakrabarty K, Tehranipoor M (2013) Crosstalk- and process variations-aware high-quality tests for small-delay defects. IEEE Trans VLSI Syst 21(6):1129–1142. https://doi.org/10.1109/TVLSI.2012.2205026

    Article  Google Scholar 

  30. Pomeranz I, Reddy SM (1994) An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. IEEE Trans Comput-Aided Des Integr Circuits Syst 13(2):240–250

    Article  Google Scholar 

  31. Qiu W, Wang LC, Walker D, Reddy D, Lu X, Li Z, Shi W, Balachandran H (2004) K longest paths per gate (klpg) test generation for scan-based sequential circuits. In: 2004 Proceedings of the internationaltest conference. https://doi.org/10.1109/TEST.2004.1386956, pp 223–231

  32. Sato Y, Hamada S, Maeda T, Takatori A, Nozuyama Y, Kajihara S (2005) Invisible delay quality-sdqm model lights up what could not be seen. In: 2005 IEEE Proceedings of the IEEE International Test Conference, pp 9–pp

  33. Sauer M, Becker B, Polian I (2016) Phaeton: a sat-based framework for timing-aware path sensitization. IEEE Trans Comput 65(6):1869–1881. https://doi.org/10.1109/TC.2015.2458869

    Article  MathSciNet  Google Scholar 

  34. Smith GL (1985) Model for delay faults based upon paths. In: Proceedings of the international Test Conference, pp 342–351

  35. Synopsys (2018) Design compiler

  36. Tayade R, Abraham J (2008) Small-delay defect detection in the presence of process variations. Microelectronics J 39(8):1093–1100. https://doi.org/10.1016/j.mejo.2008.01.003, european Nano Systems (ENS) 2006

    Article  Google Scholar 

  37. Tayade R, Abraham JA (2008) On-chip programmable capture for accurate path delay test and characterization. In: 2008 Proceedings of the IEEE International Test Conference, IEEE, pp 1–10

  38. Tendolkar N (1985) Analysis of timing failures due to random AC defects in VLSI modules. In: 1985 Proceedings of the 22nd conference on design automation. https://doi.org/10.1109/DAC.1985.1586020, pp 709–714

  39. Wagner M, Wunderlich HJ (2017) Probabilistic sensitization analysis for variation-aware path delay fault test evaluation. In: 2017 Proceedings of the 22nd IEEE European Test Symposium (ETS). https://doi.org/10.1109/ETS.2017.7968226, pp 1–6

  40. Waicukauski J, Lindbloom E, Rosen BK, Iyengar V (1987) Transition fault simulation. IEEE Des Test Comput 4(2):32–38. https://doi.org/10.1109/MDT.1987.295104

    Article  Google Scholar 

  41. Xiang D, Li J, Chakrabarty K, Lin X (2013) Test compaction for small-delay defects using an effective path selection scheme. ACM Trans Des Autom Electron Syst 18(3):44:1–44:23. https://doi.org/10.1145/2491477.2491488

    Article  Google Scholar 

  42. Xiang D, Shen K, Bhattacharya BB, Wen X, Lin X (2016) Thermal-aware small-delay defect testing in integrated circuits for mitigating overkill. IEEE Trans Comput-Aided Des Integr Circuits Syst 35(3):499–512. https://doi.org/10.1109/TCAD.2015.2474365

    Article  Google Scholar 

  43. Xu D, Li H, Ghofrani A, Cheng KT, Han Y, Li X (2014) Test-quality optimization for variable-detections of transition faults. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (8):1738–1749. https://doi.org/10.1109/TVLSI.2013.2278172

    Article  Google Scholar 

  44. Yilmaz M, Chakrabarty K, Tehranipoor M (2010) Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits. IEEE Trans Comput-Aided Design Integr Circuits Syst 29(5):760–773. https://doi.org/10.1109/TCAD.2010.2043591

    Article  Google Scholar 

  45. Yoneda T, Hori K, Inoue M, Fujiwara H (2011) Faster-than-at-speed test for increased test quality and in-field reliability. In: Proceedings of the 2011 IEEE International Test Conference. https://doi.org/10.1109/TEST.2011.6139131, pp 1–9

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Acknowledgments

The authors would like to thank CMC Microsystems and CMP for providing the CAD tools and access to a 28nm PDK, Octasic for providing partial financial support and scientific guidance, and the Natural Science and Engineering Research Council for providing partial funding.

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Correspondence to Omar Al-Terkawi Hasib.

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Al-Terkawi Hasib, O., Savaria, Y. & Thibeault, C. Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. J Electron Test 35, 823–838 (2019). https://doi.org/10.1007/s10836-019-05832-w

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