Abstract
We propose an architecture for a Field Programmable Gate Array (FPGA) based tester for a 3D stacked integrated circuit (IC). Due to the very short distances between dies in a stack that can make SerDes connections very efficient and the high density of through silicon vias (TSVs) that may be available, it is possible to connect the FPGA to the die under test through a very high bandwidth connection that can feed multiple short scan chains. We propose and evaluate two designs that exploit the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns, reducing the FPGA resources required and the switching activity in the circuit under test when compared to a more traditional on-chip decompressor implemented to feed short scan chains. For the largest circuit we studied, the switching activity was reduced about 80% and the test time by 90%.
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Notes
In order to achieve high test coverage, the number of top off patterns could be quite significant. Exploring how to decrease the top-off patterns is left for future work.
By uncompressed, we mean the patterns are generated without an on-chip decompressor, but still after the dynamic pattern compression from the ATPG tool.
Note that the length of the scan chain can have a bearing on the number of patterns produced from an on-chip decompressor [4] with larger chains leading to fewer patterns.
References
Agrawal M, Chakrabarty K (2013) Test-cost optimization and test-flow selection for 3d-stacked ics. In: Proc IEEE 31st VLSI Test Symposium (VTS), pp 1–6. https://doi.org/10.1109/VTS.2013.6548941
Aleksejev I, Devadze S, Jutman A, Shibin K (2015) Virtual reconfigurable scan-chains on fpgas for optimized board test. In: Proc 16th Latin-american Test Symposium (LATS), pp 1–6. https://doi.org/10.1109/LATW.2015.7102411
Alfke P (1996) Efficient shift registers, LFSR counters, and long pseudorandom sequence generators. Tech. rep., Xilinx. https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf/
Chakravadhanula K, Chickermane V, Cunningham P, Foutz B, Meehl D, Milano L, Papameletis C, Scott D, Wilcox S (2017) Advancing test compression to the physical dimension. In: Proc IEEE International Test Conference (ITC), pp 1–10. https://doi.org/10.1109/TEST.2017.8242035
Chandra A, Kapur R (2008) Bounded adjacent fill for low capture power scan testing. In: Proc 26th IEEE VLSI Test Symposium (VTS), pp 131–138. https://doi.org/10.1109/VTS.2008.47
Chaware R, Nagarajan K, Ramalingam S (2012) Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer. In: Proc IEEE 62nd Electronic Components and Technology Conference, pp 279–283. https://doi.org/10.1109/ECTC.2012.6248841
Claus C, Ahmed R, Altenried F, Stechele W (2010) Towards rapid dynamic partial reconfiguration in video-based driver assistance systems. In: Sirisuk P, Morgan F, El-Ghazawi T, Amano H (eds) Reconfigurable Computing: Architectures, Tools and Applications. Springer, Berlin, pp 55–67
Crouch AL, Potter JC, Khoche A, Dworak J (2013) Fpga-based embedded tester with a p1687 command, control, and observe-system. IEEE Des Test 30(5):6–14. https://doi.org/10.1109/MDAT.2013.2278531
Debany WH, Gorniak MJ, Daskiewich DE, Macera AR, Kwiat KA, Dussault HB (1992) Empirical bounds on fault coverage loss due to LFSR aliasing. In: Proc IEEE VLSI Test Symposium, pp 143–148. https://doi.org/10.1109/VTEST.1992.232739
Deutsch S, Keller B, Chickermane V, Mukherjee S, Sood N, Goel SK, Chen J, Mehta A, Lee F, Marinissen EJ (2012) Dft architecture and ATPG for interconnect tests of JEDEC wide-I/O memory-on-logic die stacks. In: Proc IEEE International Test Conference (ITC), pp 1–10. https://doi.org/10.1109/TEST.2012.6401569
Devadze S, Jutman A, Aleksejev I, Ubar R (2009) Fast extended test access via JTAG and FPGAs. In: Proc International Test Conference, pp 1–7. https://doi.org/10.1109/TEST.2009.5355668
Dorsey P (2010) White paper: Xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity, bandwidth, and power efficiency. Tech. rep., Xilinx
Fkih Y, Vivet P, Rouzeyre B, Flottes M, Di Natale G (2013) A JTAG based 3D DfT architecture using automatic die detection. In: Proc 9th Conference on ph.d. Research in Microelectronics and Electronics (PRIME), pp 341–344. https://doi.org/10.1109/PRIME.2013.6603184
Lau JH, Yue TG (2009) Thermal management of 3D IC integration with TSV (through silicon via). In: Proc 59th Electronic Components and Technology Conference, pp 635–640. https://doi.org/10.1109/ECTC.2009.5074080
Loeblein M, Tsang SH, Han Y, Zhang X, Teo EHT (2016) Heat dissipation enhancement of 2.5D package with 3D graphene and 3D boron nitride networks as thermal interface material (TIM). In: Proc 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), pp 707–713. https://doi.org/10.1109/ECTC.2016.85
Manoj PDS, Lin J, Zhu S, Yin Y, Liu X, Huang X, Song C, Zhang W, Yan M, Yu Z, Yu H (2017) A scalable network-on-chip microprocessor with 2.5d integrated memory and accelerator. IEEE Trans Circuits Syst I, Reg Papers 64(6):1432–1443. https://doi.org/10.1109/TCSI.2016.2647322
Mitra S, Kim KS (2002) X-compact: an efficient response compaction technique for test cost reduction. In: Proc International Test Conference (ITC), pp 311–320. https://doi.org/10.1109/TEST.2002.1041774
Rajski J, Tyszer J, Kassab M, Mukherjee N, Thompson R, Tsai K-h, Hertwig A, Tamarapalli N, Mrugalski G, Eide G, Qian J (2002) Embedded deterministic test for low cost manufacturing test. In: Proc International Test Conference (ITC), pp 301–310. https://doi.org/10.1109/TEST.2002.1041773
Roy SK, Ghosh P, Rahaman H, Giri C (2014) Session based core test scheduling for 3D SOCs. In: Proc IEEE Computer Society Annual Symposium on VLSI, pp 196–201. https://doi.org/10.1109/ISVLSI.2014.61
Sperling E Is the 2.5D supply chain ready? Semiconductor Engineering https://semiengineering.com/is-the-stacked-die-supply-chain-ready/ Accessed: 2019-11-26
Sperling E Thinking outside the chip. Semiconductor Engineering https://semiengineering.com/thinking-outside-the-chip/ Accessed: 2019-11-26
Wang C, Zhou J, Weerasekera R, Zhao B, Liu X, Royannez P, Je M (2015) Bist methodology, architecture and circuits for pre-bond tsv testing in 3d stacking ic systems. IEEE Trans Circuits Syst I, Reg Papers 62(1):139–148. https://doi.org/10.1109/TCSI.2014.2354752
Wu X, Falkenstern P, Chakrabarty K, Xie Y (2009) Scan-chain design and optimization for three-dimensional integrated circuits. J Emerg Technol Comput Syst 5(2):9:1–9:26. https://doi.org/10.1145/1543438.1543442
Xie J, Patterson D (2013) Realizing 3D IC integration with face-to-face stacking. Chip Scale Review 17 (3):16–19
Xilinx: 3D ICs. https://www.xilinx.com/products/silicon-devices/3dic.html. Accessed: 2019-07-27
Xilinx: UG 474: 7 series FPGAs configurable logic block user guide. https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf. Accessed: 2019-06-17
Zhang F, Sun Y, Shen X, Nepal K, Dworak J, Manikas T, Gui P, Bahar RI, Crouch A, Potter J (2016) Using existing reconfigurable logic in 3D die stacks for test. In: Proc IEEE 25th North Atlantic Test Workshop (NATW), pp 46–52. https://doi.org/10.1109/NATW.2016.15
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This work was supported in part by NSF grant CCF-1814928 and CCF-1812777.
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Sun, Y., Zhang, F., Jiang, H. et al. Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J Electron Test 35, 887–900 (2019). https://doi.org/10.1007/s10836-019-05845-5
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DOI: https://doi.org/10.1007/s10836-019-05845-5