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Trojan Detection Test for Clockless Circuits

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Abstract

Clockless integrated circuits, as any type of integrated system, might today carry hardware Trojan (HT) circuits maliciously implanted in the designs during outsourced phases of fabrication. This paper proposes a testing technique dedicated to detect HTs in clockless circuits fabricated in CMOS technologies. The proposed technique applies a well-known machine learning approach – One-Class Support Vector Machine (OC-SVM) – for dealing with the particular current signature features of clockless circuits. Through simulation experiments we show the natural ability of clockless circuits in providing individual current signatures for identifying the presence of HTs. Moreover, the results demonstrate that our testing technique requires no extra circuitry or power ports to detect HTs of a few dozens of transistors in designs under Trojan test with more than 13 thousand transistors.

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Correspondence to Ricardo Aquino Guazzelli.

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Responsible Editor: S. Bhunia

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Guazzelli, R.A., Trindade, M.G., Guimarães, L.A. et al. Trojan Detection Test for Clockless Circuits. J Electron Test 36, 23–31 (2020). https://doi.org/10.1007/s10836-020-05857-6

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  • DOI: https://doi.org/10.1007/s10836-020-05857-6

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