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Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures

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Abstract

This article analyzes and rationalizes the capabilities of inversion test points (TPs) when implemented in lieu of traditional test point architectures. With scaling transistor density, logic built-in self-test (LBIST) quality degrades and additional efforts must keep LBIST quality high. Additionally, delay faults must be targeted by LBIST, but delay faults can be masked when using control-0/1 (i.e., traditional) TP architectures. Although inversions as TPs have been proposed in literature, the effect inversion TPs have on fault coverage compared to traditional alternatives has not been explored. This study extends work previously presented in the North Atlantic Test Workshop (NATW’19) and finds both stuck-at and delay fault coverage improves under pseudo-random tests using inversion TPs, and extended data collection finds noteworthy trends on the effectiveness of TP architectures.

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Authors and Affiliations

  1. Auburn University, Auburn, AL, 36849, USA

    Soham Roy, Spencer K. Millican & Vishwani D. Agrawal

  2. Nvidia, Madison, AL, 35748, USA

    Brandon Stiene

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  1. Soham Roy
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  2. Brandon Stiene
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  3. Spencer K. Millican
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  4. Vishwani D. Agrawal
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Correspondence to Spencer K. Millican.

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Responsible Editor: T. Xia

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Roy, S., Stiene, B., Millican, S.K. et al. Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures. J Electron Test 36, 123–133 (2020). https://doi.org/10.1007/s10836-020-05859-4

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  • DOI: https://doi.org/10.1007/s10836-020-05859-4

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