Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors
Graphical abstract
The short-channel performance of bulk TFETs is not influenced by the HGD engineering, but the use of HGDs increases SCEs in double-gate TFETs. The SCEs in HGD double-gate TFETs can be improved by locating the drain-side heterojunction toward the drain and/or increasing the low/high-k EOT ratio.
Introduction
The low power consumption of integrated circuits has become one of the most concerns in the era of portable electronic devices. To use energy efficiently, steep slope transistors are expected to allow scaling of supply voltage while still maintaining reasonable operating speed. While metal-oxide-semiconductor field-effect transistors (MOSFETs) exhibit the fundamental kT/q limit, tunnel field-effect transistors (TFETs) have emerged as a potential candidate due to the ability of TFETs in breaking through the MOSFETs’ limit of 60 mV/decade subthreshold swing at room temperature [1,2]. However, the mechanism of band-to-band-tunneling (BTBT), which helps TFETs to achieve a sub-60 mV/decade subthreshold swing, is also the cause of low on-current in TFETs [3]. Since the tunneling probability is strongly inversely proportional to the height of tunnel barrier, low-bandgap materials, such as SiGe and InGaAs, have been used to effectively boost the TFET current [4,5]. To further enhance the on-current, low-bandgap semiconductors have been incorporated in advanced TFET structures [6,7]. In the other hand, the inherent ambipolar behavior always exists in TFETs because the source- and drain-channel junctions can all play the role of tunnel junctions [8]. Regarding to the enhancement of on-current and the suppression of ambipolar leakage, lots of different techniques have been proposed and investigated [7,[9], [10], [11], [12]]. Among them, the hetero-gate dielectric (HGD) engineering, which combines material and structural techniques, has demonstrated the benefits in both on-current and ambipolar current [9,13].
Once the power consumption is largely reduced, the size of transistors can be further scaled down without the problems of power density in integrated circuits. In this circumstance, one of the main challenges is to maintain a favorable on-off switching of transistors while decreasing their size. Since the density of transistors is highly associated with the scaling of gate/channel length [14], the short-channel effect is a critical issue of TFET devices. Moreover, the downsizing of TFETs is also a crucial task to make them competitive with conventional MOSFETs, which can be potentially scaled down to a 6-nm channel length [15]. Similar to the mechanism of drain-induced barrier lowering (DIBL) in MOSFETs, the penetration of the drain field into the channel region in short-channel TFETs thins the tunnel barrier and causes an effect called drain-induced barrier thinning (DIBT) [16]. The SCEs of TFETs depend on many factors, such as equivalent oxide thickness (EOT) [17], drain doping [18], gate-drain alignment [19], semiconductor parameters [20], and semiconductor heterojunctions [21]. While the hetero-structure technique of body materials greatly suppresses SCEs [21], the influence of the hetero-structure engineering of gate dielectrics on SCEs in TFETs still remains unclear. Recently, many studies have applied the HGD engineering to improve the on- and off-currents of TFETs [22,23]. Therefore, an adequate understanding on the HGD influence on SCEs in TFETs is necessary.
In this paper, the influence of HGDs on SCEs in TFET devices was investigated using the TCAD simulations of two-dimensional devices [24]. All TFETs were based on direct-bandgap In0.53Ga0.47As with a relatively low bandgap (0.75 eV). SCEs were primarily considered in terms of off-current, subthreshold swing and DIBT, which are the most typified factors of short-channel TFET performance. To elucidate the HGD influence on the SCEs, the SCEs of hetero- and uniform-gate dielectric (UGD) TFETs were studied and compared properly. For each type of gate-insulator layers, both bulk and double-gate (DG) structures of TFETs were considered. The mechanism of HGDs as well as the effects of HGD parameters on the SCEs in TFETs were explained and discussed adequately. The paper consists of five main sections, including the introduction and conclusion sections. After describing simulation models in section 2, the structure-dependent influence of HGDs on the SCEs is presented in Section 3. Section 4 clarifies the mechanism of HGDs on the SCEs while Section 5 is devoted to address the effects on the SCEs of the basic HGD parameters including the heterojunction position and low/high-k EOT ratio.
Section snippets
Simulation models
The electrical characteristics of transistors are obtained by self-consistently solving Poisson's equation and continuity equations using the Boltzmann transport theory for electrons and holes in the two-dimensional simulations [24]. For MOSFETs, the conduction current is based on the thermal diffusion, which is included in the drift-diffusion carrier transport equations. However, the conduction current of TFETs is created by charge carriers that are generated by the BTBT mechanism. The
Structure-dependent influence of HGD on SCEs
In principle, the primary purpose of designing the gate-insulator layer is to increase the gate control on the channel region. Normally, the stronger the coupling between the gate and channel is, the better is the performance of devices. Because the gate control capability depends not only on the thickness of the gate insulator but also on the size of the channel region, the influence of HGDs on the SCEs is predicted to be dependent on the device structure. In this section, we showed the
Influence mechanism of HGD on SCEs
Similar to the introduction of the hetero-body semiconductor into TFETs, the idea of the hetero-gate dielectric is also based on the fact that the on-state tunneling takes place at the source-channel junction whereas the off-state tunneling is at the drain-channel junction. The gate dielectric at the source side has a high k-value to enhance the on-state tunneling whereas that at the drain side has a low k-value to attain a low ambipolar tunneling current [42]. However, the SCEs in TFETs are
Effects of HGD parameters on SCEs
The important parameters that are concerned in designing the HGD layer of TFETs include the low/high-k EOT ratio and the positions of dielectric heterojunctions at the source/drain sides. For the role of the gate-dielectric layer in determining the electrical characteristics of TFETs, only the dielectric part near the source-channel junction determines the on-current, whereas the ambipolar off-current is also determined only by the dielectric part near the drain-channel junction. Differently
Conclusion
The influence of the HGD structure on the SCEs in TFETs was explored to allow a comprehensive evaluation on the role of the HGD engineering in determining the short-channel performance of devices. Although the HGD helps to improve the on-current, it also increases the SCEs in short-channel TFETs. The HGD influence on the SCEs is considerable in double-gate TFETs, but negligible in bulk devices. An adequate investigation of the effects of the HGD parameters, including the heterojunction position
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgments
This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 103.02-2018.309. This work is also supported by Dalat University of Vietnam, the Ministry of Science and Technology and the National Center for High-Performance Computing of Taiwan.
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