Serial concatenated convolutional code encoder in quantum-dot cellular automata

Abstract

Quantum-dot cellular automata (QCA) are a prospective nanotechnology with striking performance for complementing complementary metal oxide semiconductor (CMOS) based integrated circuit technique. For applications in communications, serial concatenated convolutional codes (SCCCs) have been investigated due to their negligible error floor for deep space communication. Using a combination of top-down and bottom-up approaches, we design and implement an SCCC encoder in QCA technology. In this work, a Bose–Chaudhuri–Hocquenghem (BCH) code encoder with the ability for correcting burst errors, a pseudo random interleaver for permuting signal bits, and a convolutional code encoder for correcting random errors are logically connected in series for composing the SCCC encoder. Specifically, inspired by the idea for a divider design, a layout for (n, k, t) BCH code encoders is proposed and implemented with QCA cells. For using the four-phase clock mechanism, we also devise the serial-to-parallel and parallel-to-serial converters for constructing the interleaver. In addition, (u, f, K) convolutional code encoders with various constraint lengths are designed as well. The functionalities and validity of the proposed circuit design are verified by using QCADesigner.

Introduction

Quantum-dot cellular automata (QCA) offer a computing paradigm and information transmission pattern in the nanometer regime [1]. Binary information is represented by the positions of electrons in a cell that consists of four quantum dots and two free mobile electrons. The information is then transmitted by purely field-coupled interaction between cells [2]. By this means, there is no current flow in QCA circuits, so that it enables systems with extremely low energy dissipation [3]. Along with ultrahigh integration and processing speed, these performance merits make QCA a hopeful candidate for complementing complementary metal oxide semiconductor (CMOS) based integrated circuits [4], [5], [6]. Additionally, to correctly control signal flow in complex circuits, a quasi-adiabatic switching mechanism was introduced to QCA, resulting in four cyclic clock zones, each of which is composed of four phases (switch, hold, release and relax), respectively [7]. Therefore, a binary string will successively transmit through cells defined in these zones.

The design methodology for a QCA system was derived from the automated CMOS design process [8]. Majority-based logic synthesis techniques were put forward to reduce the number of operational components, leading to optimized and efficient systems [9], [10]. Meanwhile, basic arithmetic and memory circuits were realized as well [11], [12], [13]. However, the wiring in a system heavily relies on the adopted clock scheme. Two-dimensional and Universal-Scalable-Efficient (USE) clocks provide preferable solutions at present [14], [15]. One can use a basic clock for any circuit to ensure the synchronization of signals arriving at the same device [16]. Naturally, related evaluation criteria for variable circuits, such as the cost and power dissipation, were proposed to select the best scheme [17], [18]. It is worth mentioning that nanomagnet logic and molecular QCA may be more promising in physical implementation because of their ambient working temperature [19], [20].

In order to achieve reliable data transmission and communication, coding circuits are crucial. Error correcting codes typically include block codes (BCs) and convolutional codes (CCs). Specifically, BCs (including Hamming codes, low density parity check (LDPC) codes, and Bose–Chaudhuri–Hocquenghem (BCH) codes) split a long message into independent fragments and separately encode them by adding specific parity bits into each fragment. Hamming code encoders and LDPC code decoders were already designed with QCA [21], [22], [23]. BCH codes are one of the most important cyclic codes for correcting multiple burst errors and widely used in fiber-optical communication and satellite communication systems. The codeword for BCH codes is usually generated by linear feedback shift registers (LFSRs) in conventional circuits. To the best of our knowledge, BCH codes have not been studied in QCA technology.

CCs differ from BCs in that the parity bits are not only related to the current bits but also involving former K $+$ 1 fragments, where K $+$ 1 indicates the constraint length of the operational CC encoder. Three schemes for rate-1/2 and constraint length-3 CC encoders were presented [24] to directly map conventional circuits to QCA with a high cost. In addition, Turbo codes or parallel concatenated convolutional codes (PCCCs) make it possible to approach the Shannon limit in terms of bit error rate (BER) [25]. Turbo code encoders using parallel concatenated recursive CC encoders and an interleaver were also investigated in QCA and simulated by hardware description language for QCA (HDLQ) [26]. A component in an interleaver is a serial-to-parallel converter [22], [26], [27]. Although these designs seem to be simple in QCA, an additional special clock was applied to keep some cells in the Relax phase to complete signal transmission, which violets the four-phase clock mechanism and results in complex clock wiring under the QCA substrate layer. Furthermore, with increasing signal-noise ratio (SNR), the BER of PCCCs may not continue to decrease, reaching the so-called error floor. Consequently, serial concatenated convolutional codes (SCCCs) were invented to provide superior error-free performance [28]. In some cases, SCCCs can be considered as a credible or superior replacement for PCCCs. One can find further theoretical basics and comparisons in [28]. SCCC encoders were widely used in deep space communication due to their negligible error floor by employing serially concatenated BC and CC encoders.

In this paper, we propose designs of SCCC encoders in QCA and verify the designs by simulation. The main contributions of this work are as follows:

$•$ A framework for designing SCCC encoders is developed by using QCA cells for the first time.

$•$ Using the four-phase clock mechanism in QCA, we devise a new scalable serial-to-parallel converter and an expandable parallel-to-serial converter.

$•$ A scalable interleaver is designed with the aforementioned two converters, which can also be used as a Last-In-First-Out (LIFO) converter.

$•$ Abandoning the LFSR structure, we propose a layout for BCH code encoders by applying coplanar XOR gates, and then implement encoders with various error correcting capabilities in QCA.

$•$ The CC encoders with various constraint lengths are designed with XOR gates.

$•$ The functionalities and validity of presented circuits are demonstrated with QCADesigner.

$•$ The QCA costs for BCH code and CC encoders are calculated and summarized.

This paper proceeds as follows: the background for QCA, including basic devices and clock mechanism, is briefly reviewed in Section 2. Section 3 presents the rationale of SCCC encoders in detail. Each component and the full circuit of an SCCC encoder are then designed in QCA in Section 4. Simulation results are presented in Section 5. Finally, Section 6 concludes this paper.