Low-overhead thermally resilient optical network-on-chip architecture

Abstract

Integrated silicon photonic networks have attracted a lot of attention in the recent decades due to their potentials for low-power and high-bandwidth communications. However, these promising networks, as the future technology, are drastically susceptible to thermal fluctuations, which may paralyze wavelength-based operation of these networks. In this regard, precise addressing of thermally induced faults in optical networks-on-chip (ONoCs), as well as revealing practical methods to tackle this challenge will be a break-even point toward implementation of this technology. In this paper, thermal variation is investigated through analyzing on-chip power distribution, which is addressed by power profile of SPEC 2006 benchmark applications. Based on these assessments, herein we propose a low-power thermal-resilient optical network-on-chip (The-RONoC) architecture that significantly mitigates routing faults in ONoC. Utilizing a corrective unit in this architecture, 50% of the thermally induced switching faults are recovered with the cost of less than 2% area overhead. In addition, up to 42% performance improvement is achieved through this architecture in comparison to the basic architecture. Finally, we explore scalability of The-RONoC based on formal SNR analysis, as well as power consumption and the probability of optical transmission speed-up.

Introduction

Network-on-chips (NoCs) as the state-of-the-art high-performance interconnection systems, pave the way toward high degree of parallelism and fast communications throughout the chip [1]. However, with the ever-increasing demand for low-power and high-bandwidth interconnection, electrical NoCs (ENoCs) meet the performance and power walls as the number of interconnected cores increases. To tackle these challenges, silicon photonic interconnections are proposed as a promising paradigm with low-power and high-bandwidth communication potentials [2], [3]. The feasibility to exploit optical NoC (ONoC) relies upon the latest achievements in CMOS fabrication process, in particular, Silicon-on-Insulator (SOI) technology [4].

Although ONoCs are the breakthrough technology advancement in high-performance systems, their wavelength-based operation is severely susceptible to temperature fluctuation [5]. Generally, temperature drifts affect all the optical components, although active components such as microring resonators (MRs) have much higher failure rate than passive components such as waveguides. The refractive index of the optical devices changes with temperature drift. In particular, the resonant wavelength of a MR, as a building block of many conventional ONoCs [6], varies with thermal variations [7]. As a result of this thermo-optical effect, the shifted resonant wavelength of the MR resulting in partial or even complete pass-band mismatch, resulting in misrouting of optical data passing through the heated MR. It is worth noting that, the resonant wavelength of a microring resonator shifts by 0.11 nm/°C, which leads to a partial, or even complete pass-band mismatch [4]. In other words, for a microring resonating at typical wavelength of 1550 nm, a temperature drift of 11.82 °C causes a resonant wavelength shift equal to 1.3 nm, which is the typical wavelength separation between two optical channels multiplexed on a waveguide, known as channel spacing. A complete mismatch between resonating wavelength of a microring and an optical data passing through it causes almost all portion of the optical power be directed through a wrong path, and almost no optical power is switched into the desired path. On the other hand, the optical power passing through the wrong path results in increased crosstalk with other optical packets modulated on the same wavelength channel. The later impact is considered while calculating SNR values for various fault scenarios. The optical power passing the wrong path results in increasing interfering other optical packets with modulated on similar wavelength. This fact is considered in SNR calculation of various studies. In this manner, the physical-level failure drastically results in network-level faults. This is not a permanent fault and can be prevented by keeping the temperature at the reasonable range, which is challenging in large and complex ONoCs.

This paper aims at assessing the potential thermally induced faults in ONoC at a higher level of abstraction, i.e. network level, to project the exclusive impact of temperature fluctuation through a more practical metric, i.e. fault rate. By pursuing the impact of thermal fluctuation on network behavior through the presented metric, we thereby propose a conceivable thermally resilient ONoC architecture, The-RONoC, which inhibits thermally-induced fault impacts by employing additional switching units. These additional units, tightened to each row of the mesh-based wavelength-routed ONoC architecture, retransmit the misrouted optical data toward the destination column. Moreover, we show that for the optical packets transmitted through an N$\times$N The-RONoC topology, the network provides communication speed-up in comparison to its earlier version called HANoC.

In terms of performance, we show that The-RONoC architecture outweighs the previously proposed thermal aware architectures in two ways; first, measuring the temperature of surface layer and/or optical layer of the chip is not required for this architecture. In this manner, we save the implementation cost as well as power overhead of on-chip thermal sensors. Second, unlike various thermal-aware techniques, the transmitter node of the misrouted optical data in The-RONoC architecture neither waits for a timeout to reach or an ack/nack packet to arrive, nor retransmits the data in an alternative path or an alternative wavelength. By this means, aside from simpler and faster retransmission mechanism obtained in The-RONoC architecture, it gains from saving the power imposed by additional opto-electrical modulation for retransmission, as well as a wider bandwidth laser source. The main contributions of this paper are summarized as follows:

• We utilize a precise heat conduction model for multilayer ONoC [8], [9] validated by HotSpot thermal simulation tool [10] in this paper. Through this precise model, we evaluate thermally-induced faults in two wavelength-routed architectures, i.e. mesh-based High-performance All-optical NoC (HANoC) architecture, and a novel thermally resilient variant of HANoC, The-RONoC.

• We propose a power-efficient The-RONoC architecture that retransmits misrouted optical data toward the destination column with low power penalties. The complexity of the optical router design is not increased and the design of the retransmission unit, as well as its layout, are simple and straightforward. As we demonstrate, the reliability improvement presented by this architecture is provided at the expense of less than 2% area overhead.

• We propose fault rate as a system-level criterion that exclusively focuses on the impact of temperature fluctuation at a practical standpoint for the designers.

• We formally evaluate area overhead, system throughput, power consumption and transmission delay for The-RONoC architecture. The results reveal that the proposed architecture is a low-overhead and low-power ONoC.

• In order to determine the scalability of The-RONoC architecture, we explore the worst-case path from the SNR perspective. In this manner, a novel hierarchical method is revealed which finds the minimum SNR in the network.

• To emphasize the impact of applications on network fault rate, we employ two categories of applications from SPEC 2006 benchmark applications [11], extract the corresponding power consumption of the processing cores, and adopt them as the heat source in the electrical layer of the chip. We address dynamic fluctuation of temperature throughout the chip, as a result of run-time power variation of processing cores.

The rest of the paper is organized as follows. First, Section 2 reviews related literature addressing the impact of thermal fluctuations in ONoCs. In Section 3, we analyze thermo-optical properties of the on-chip optical devices. In Section 4 we propose our thermally-resilient architecture and reveal its pros and cons. In Section 5, we analyze the system performance through analytical parameters. In Section 6, we explain the simulation environment and the simulation flow adopted throughout the paper. Also, various fault scenarios and simulation results are revealed in this section. Finally, the paper is concluded in Section 7.