Elsevier

Nano Communication Networks

Volume 19, March 2019, Pages 119-133
Nano Communication Networks

H2WNoC: A honeycomb hardware-efficient wireless network-on-chip architecture

https://doi.org/10.1016/j.nancom.2019.01.005Get rights and content

Abstract

Network-on-chips (NoCs) have emerged as communication backbones for enabling massive parallelism and high degree of integration in many-core chips. In spite of the advantages of conventional NoCs, wired multi-hop links impose limitations on NoCs performance by long delay and high power consumption especially in large systems. To alleviate these problems, different solutions such as wireless network-on-chip (WiNoC) designs have been proposed. WiNoCs benefit from long-range, high bandwidth and low power wireless links to solve problems corresponding to wired communications. Most of the WiNoC architectures have been designed based on mesh topology, while, honeycomb topology provides more energy-efficient NoC architecture with higher throughput than mesh topology, but, as we will show, a honeycomb-based WiNoC, by itself, does not reduce the amount of utilized hardware resources and delay. In this paper, we propose a hardware-efficient WiNoC with honeycomb topology, namely, H2WNoC aiming at reducing hardware resources, network cost, delay, and also energy consumption. Considering different performance parameters, cycle-accurate-based evaluations are performed for the proposed architecture; H2WNoC is compared with the traditional mesh WiNoC, as the baseline, and also with three state-of-the-art WiNoC architectures. Furthermore, design space exploration of the proposed architecture is performed. Performance evaluations indicate that H2WNoC utilizes less hardware resources, consumes less amount of energy and improves both throughput and delay, compared to the other WiNoC architectures. Moreover, the obtained results show that the proposed architecture outperforms wired NoCs either with mesh or honeycomb topology.

Introduction

Nowadays, digital systems with a large number of cores are implemented on a single integrated circuit known as system-on-chip (SoC). Continuing technology scaling is enabling the integration of billions of gates for each core. Placing such many cores with several on-chip processing elements in one chip allows superior performance gains, but comes with many challenges. The major challenge is to provide an efficient, low power, scalable and reliable communication among these cores. Traditionally, SoCs use point-to-point interconnections and/or buses to accommodate communication between cores. Point-to-point approach is not scalable and imposes a huge communication costs on chip especially for fine-grain, many-core SoCs. Also, bus structure can be a significant bottleneck for many-core chips, because as a large number of cores communicate simultaneously, managing sending packets and preventing collisions imposes much overhead to the whole system [1], [2], [3].

Instead of these communication fabrics, network-on-chip (NoC) architecture, a collection of cores, links, routers and network interfaces is much more efficient. NoCs can tackle many limitations associated with traditional SoC interconnections, such as clock frequency limitation and alleviating power dissipation. As a NoC can accommodate multiple flows between cores simultaneously, they are considered as the most viable communication infrastructure that provides high performance, low power and reliable many-core architectures. The main advantage of NoCs lies in the exploitation of massive parallelism, so they has been used for implementing accelerators and special purpose processing elements in different areas, such as reconfigurable computing, cloud computing, internet of things, networking, and storage applications [1], [2], [4].

Despite of the mentioned advantages, NoCs suffer from some limitations. Long transmission delay, high power consumption, and limited metal bandwidth, especially for multicasting andbroadcasting [4], [5], [6], due to planar communications across wired links are the main limitations of NoCs. Therefore, alternative communication approaches such as optical interconnections [7], radio frequency (RF) transmission lines [8], [9] and CMOS wireless communications [4], [10], [11], [12], [13] have been proposed to reduce transmission delay and power dissipation, and also to increase network throughput. However, on-chip optical interconnections have technological challenges such as designing efficient transceiver components, integration of on-chip photonic components and high manufacturing cost which will prevent its commercial adoption. Although multi-band RF can be implemented by silicon-based CMOS technology, it requires additional physically overlaid transmission lines which serve as waveguide to enable data communication. To achieve high throughput, RF based systems must utilize multiple high frequency oscillators and high precision filters to validate its feasibility. NoC architectures with hybrid wired and wireless links called wireless network-on-chip (WiNoC) [4], [5], [6], [14], [15], [16], [17], [18], [19], [20], [21]. It uses existing CMOS technology to replace long-latency wired communication links with express long-range wireless channels, so that transmission performance and power consumption problems in conventional wired NoCs can be addressed simultaneously. In practice, beyond a certain length, wireless links consume less amount of energy than conventional metal wires, therefore, the performance improvements utilizing long-range wireless links will be much more than that using wired links [8].

From architectural point of view, mesh topology is simple, regular, and scalable, providing almost more efficient performance in comparison with other 2D topologies. Moreover, mesh structure is very adaptive to the structures of programmable and reconfigurable devices such as FPGAs. That is why most of the emerging WiNoC architectures have been designed based on mesh topology [16], [17], [18], [19], [20], [22], [23], [24]. On the other side, the research of [25], [25], [26], [27], [28], [29] have shown that NoCs with honeycomb topology provide better performance characteristics, in terms of energy consumption, area, delay and throughput, compared to a wired mesh NoC. HoneyWiN [28] is a honeycomb-based NoC with hybrid wired/wireless interconnections aiming at energy-efficiency. However, HoneyWiN does not improve delay and throughput regards to a mesh WiNoC. Additionally, HoneyWiN utilizes more amount of hardware resources than the mesh WiNoC [28], [29] .

In this article, we propose H2WNoC, a honeycomb-based wireless network-on-chip architecture, aiming at optimizing hardware resources utilization, delay, power consumption, and throughput, more efficiently than the other recent WiNoC architectures. In H2WNoC, an underlying wired NoC with honeycomb topology is designed, then it is augmented with wireless routers (WRs) at the same level. This approach optimizes hardware utilization, and consequently reduces power consumption and delay. Because, in H2WNoC, the WRs are placed instead of some wired based routers (BRs) while in the other WiNoC architectures, in order to design hybrid wired/wireless NoC architectures, all the underlying BRs are kept in their places, and WRs are placed at the second level.

In addition to optimizing of WR placement, we focus on reducing hardware components that cause delay in packet transmission and waste energy, such as wired links, ports, buffers and routers. The proposed strategy is performed in such ways that do not decrease the network throughput. We evaluate the effects of halving the input and output buffers for all the routers, which results a reduction in energy consumption and area, and also in propagation delay, without any penalty cost of network throughput.

For performance evaluation, we perform a detailed cycle-accurate-based analysis of H2WNoC in terms of throughput, power consumption, area, delay, and also network cost. The results indicate that H2WNoC provides higher performance than a traditional mesh WiNoC, as the baseline, and also three recent WiNoC architectures (HoneyWiN [28], [29], HiWa [24] and amsWNoC [30]). Moreover, to show the efficiency of H2WNoC, it is compared with traditional wired mesh NoC and wired honeycomb NoC. Meanwhile the performance evaluation, the design space of H2WNoC is explored to find the optimal number of WRs, number of buffers, and also efficient flit size for specific number of cores.

The remainder of this paper is organized as follows: Related studies are discussed in Section 2. The proposed architecture, H2WNoC, including the considerations of WR placement and routing approach, is expounded by Section 3. Then, Section 4 presents the methodology and performance evaluation including results and discussions, analysis of network cost, design space exploration of H2WNoC, and also comparison of the proposed architecture with some recent NoC architectures. Finally, the paper is concluded by Section 5.

Section snippets

Related work

The limitations and challenges associated with existing NoC architectures are elaborated in [31]. Recent progresses in VLSI have permitted the integration of tiny transceivers antennas on a single chip, which results in introducing WiNoCs. On-chip wireless interconnection was first proposed to distribute global clock signals in [32], because high-performance systems face critical issues on delivering power-efficient and globally interconnected clock networks. Conventional metal-based wired

The proposed architecture (H2 WNoC)

Basically, in hybrid WiNoC architectures, the network is divided into subnets where intra-subnet, communications are performed through wired links, while inter-subnet communications are almost handled by wireless waves. Hybrid WiNoCs include several wireless routers (WRs), in addition to the base wired routers (BRs) of a traditional NoC. Each WR is a multi-port router equipped with a transceiver having the capability of both wired and wireless communications. The wired port of a WR can be

Performance evaluation

In this section, the proposed architecture, H2WNoC is evaluated and compared with several different NoC configurations including the traditional the mesh WiNoC (as the baseline), three recent WiNoC architectures and with two wired NoCs one with mesh and the other with honeycomb topology.

Conclusion

Wireless network-on-chips fulfill system feasibility and flexibility to overcome limitation of wired NoCs using existing CMOS technology. In a WiNoC, multi-hop wired links have been replaced with high-bandwidth and long range wireless links. So that, transmission performance, power consumption and long distant communication problems of wired NoCs can be addressed simultaneously. In this paper, we proposed hardware-efficient honeycomb-based WiNoC (H2WNoC), aiming at reducing hardware resources,

Mohammad Alaei is an assistant professor at the department of Computer Engineering in Vali-e-Asr University of Rafsanjan, Iran. He performed his Ph.D. studies on wireless multimedia sensor networks in Universitat Politecnica de Catalonya (UPC), Spain during the years 2008–2013. He received his M.Sc. and B.Sc. in computer engineering respectively from University of Isfahan (2002), and Shahid Beheshti University (1998) in Iran. His current research interests include Collaborative In-network

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  • Cited by (0)

    Mohammad Alaei is an assistant professor at the department of Computer Engineering in Vali-e-Asr University of Rafsanjan, Iran. He performed his Ph.D. studies on wireless multimedia sensor networks in Universitat Politecnica de Catalonya (UPC), Spain during the years 2008–2013. He received his M.Sc. and B.Sc. in computer engineering respectively from University of Isfahan (2002), and Shahid Beheshti University (1998) in Iran. His current research interests include Collaborative In-network Processing, Energy Efficiency and Node Management in Wireless Network on Chip and Wireless Sensor Networks.

    Fahimeh Yazdanpanah is an assistant professor with the department of Computer Engineering in Vali-e-Asr University of Rafsanjan, Iran. She did her Ph.D. program in the field of Computer architecture in Universitat Politecnica de Catalunya (UPC), Barcelona, Spain (2008–2014). She was a researcher at the Barcelona Supercomputing Center (BSC-CNS), Spain for about 4 years. Her research interests include Wireless Communication Systems, Energy Efficiency, Wireless Network on Chip, Hardware Design of Communication Systems, Reconfigurable Architecture, FPGA-Based Design and Parallel Processing.

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