Configurable DSI partitioned approximate multiplier

Highlights

• It is error-configurable and based on lack of partial products generation for LSBs.

• It provides a trade-off between hardware resources, accuracy, delay and power.

• The goal is to reduce all hardware metrics besides keeping accuracy satisfaction.

• Many error metrics, test cases, and architectures have been used to validate our evaluations.

Abstract

Approximate computing has been considered for error-tolerant applications that can tolerate some loss of accuracy. It improves metrics such as dynamic power, delay, and area. Multipliers are key elements in arithmetic logic units and used in many applications such as Digital Signal Processing (DSP). Hence, it is vital to develop a robust strategy to take advantage of approximate computing in multipliers. In this paper, a novel algorithm has been presented for the approximate multiplication of unsigned numbers. The proposed approach is error-configurable and provides a trade-off between hardware resources, accuracy, delay, and power. In addition, it can be adjusted based on target systems or applications. The proposed method, compared to the accurate and other configurable algorithm instances, improves the metrics by using a low power configuration. Meanwhile, according to experimental results, the average error rates is 1.04% for 16-bit multiplication. The percentage of improvements for error, delay, area, and dynamic power of the proposed 16-bit multiplier are 0.02% to 16.71%, 23.8% to 70.6%, -11% to 34.1%, and 42.9% to 81.1%, respectively. Moreover, the proposed multiplier has been employed in Discrete Cosine Transform (DCT) applications and has obtained admirable outputs.

Introduction

In recent years, the CMOS technology is moving towardsmaller geometries, and the size of a transistor is considerably getting shrunk. In this regard, the number of transistors in a chip has reached billions and the complexity of recent CMOS integrated circuits has increased. Also, the newer circuits operate at higher frequencies and lower power supply and subthreshold voltages. Accordingly, power consumption grows in high density chips and it becomes a major concern in highly integrated nanoscale designs. Furthermore, the ever-increasing demand for higher computing power represents a driving force toward ultra-low power design strategies. Seeking the energy efficiency improvement, designers have turned to optimization methods in several ways, from system level down to transistor device level. Many techniques are available for reducing power consumption providing a trade-off relationship between power and performance. A potential solution to lower power dissipation is to employ approximate circuit designs [1], [2], [3].

Approximate Computing [4] is an emerging trend in digital design that exploits the inherent error tolerance in many applications to gain performance enhancement in terms of area, speed and/or power by forsaking computational accuracy. Approximate computing generates inaccurate but acceptable results rather than an accurate result. It also provides low-power and small size for a design [5], [6], [7], [8]. Especially in applications that use human senses, it is suitable to apply approximate computation because people do not recognize small errors. Applications such as image processing, recognition, Digital Signal Processing (DSP), web search algorithm, machine learning and data mining are inherently error-tolerant and do not require perfect accuracy in computation. Computing units are considered as key components of modern electronic embedded devices. For these applications, approximate circuits may play an important role as a promising alternative for reducing area, power and delay in digital systems that can tolerate some loss of accuracy, thereby achieving better performance in energy efficiency [9].

Applying the approximation to the arithmetic units can be performed at different design abstraction levels including circuit, logic, and architecture levels, as well as algorithm and software layers [5]. Using approximation in arithmetic building blocks such as adders and multipliers at different design levels have been suggested in [10], [11], [12], [13], [14]. Among the arithmetic operations, the multiplication block has always been considered as a complex block that causes increasing the complexity of the design. Multipliers are the most widely executed arithmetic blocks of an ALU in a wide range of applications including multimedia, wireless communication, machine learning, data mining, etc. [15]. Multiplication is one of the most area consuming arithmetic operations in high-performance circuits and efforts aimed at improving ALU performance. Therefore, decreasing the complexity of multipliers may reduce the power consumption of the overall system. Hence, approximate multiplier design has become an important research subject in recent years [16]. A multiplier includes a few stages. Fig. 1 shows that a multiplier includes at least three stages:

• Partial products generation

• Partial products reduction

• Carry-propagate addition

Approximations in multipliers can be conducted in any of these stages [16].

The array multiplier is well known due to its regular architecture. The circuit is based on the Add and Shift algorithm. Each partial product is generated by the multiplication of the multiplicand with one multiplier bit. The partial products are shifted according to their bit orders and then added. The addition can be performed with a normal carry propagate adder. For j multiplier bits and k multiplicand, we need $j\times k$ AND gates and $\left(j-1\right)$ k-bit adders to produce a product of $j+k$ bits. Fig. 2 shows a typical organization of a 4-bit array multiplier with exact accuracy.

Most studies have focused on applying approximation on stages 2 and 3 of a multiplier, i.e., using approximate adders for adding the generated partial products. Also, the matter of configurability among researchers has received much less attention. In this paper, a novel approximate multiplier is proposed with the approach of reducing partial products i.e., applying approximation on stage 1 of a multiplier by introducing a unique truncation strategy. The proposed approximate multiplier is configurable and it can be adjusted based on the application’s requirements. Configurability of the proposed architecture provides a trade-off relationship among minimization of average error, area, delay and dynamic power.

The rest of this paper is organized as follows. Section 2 surveys prior works. In Section 3, the proposed method is described. The experimental results and application-based evaluation are presented in Section 4. Finally, Section 5 presents the conclusion and future work.