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Fatigue Crack Networks in the Die-Attach Joint of a Power Semiconductor Module During Power Cycling Testing and Effects of Test Parameters on the Joint Fatigue Life

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Abstract

The fracture mechanisms of a Sn-Ag-Cu lead-free solder joint and the effects of test parameters on power cycling life were investigated. In this study, three levels of average temperature (348, 373 and 398 K), two levels of each of current on-and-off time (2 s/10 s and 5 s/22 s), and three levels of ΔTj (75, 100 and 125 K) were used. Because the thermal expansion of the die-attach material was restrained by Si, equibiaxial tensile and compressive creep deformation occurred during power cycling. This deformation generated fatigue cracks in the central part of the die-attach joint, and the cracks connected to each other, resulting in a fatigue crack network. The fracture occupied 70% or more of the die-attach area and was the dominant factor affecting the joint’s fatigue life. As ΔTj increased, the strain energy density in the central part increased, resulting in a decrease in fatigue life. Although the strain energy density at an average temperature of 398 K decreased by about 10% compared with that at an average temperature of 348 K, the fatigue life decreased to about 40% when the average temperature increased. Continuous dynamic recrystallization occurred during power cycling, leading to fatigue failure in high-energy grain boundaries. Since continuous dynamic recrystallization tended to occur more readily at higher temperatures, the fatigue life decreased with increasing average temperature, even for the same junction temperature range ΔTj. Moreover, the area of equibiaxial tensile and compressive creep deformation in the die-attach material became larger with increasing current on-and-off times. As a result, the fracture area under long current on-and-off time conditions was increased by about 25% in comparison with that under short current on-and-off time conditions.

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Acknowledgments

This paper is based on results obtained from an international standard development project (International standardization of endurance test method of power semiconductor circuit board/heat dissipation structure joint for industrial application) commissioned by the Ministry of Economy, Trade and Industry.

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Correspondence to Yoshiharu Kariya.

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Hosoya, K., Kariya, Y., Sugimoto, H. et al. Fatigue Crack Networks in the Die-Attach Joint of a Power Semiconductor Module During Power Cycling Testing and Effects of Test Parameters on the Joint Fatigue Life. J. Electron. Mater. 49, 6175–6186 (2020). https://doi.org/10.1007/s11664-020-08381-7

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