Full Range Capacitor Voltage Balance PWM Strategy for Diode-Clamped Multilevel Inverter

Abstract

This paper briefly reviews virtual space vector pulse width modulation (VSVPWM) for the diode-clamped multilevel inverter (DCMLI). Based on the universal modulation model of the DCMLI with N-level, a modulation strategy named as full range capacitor voltage balance PWM (FRCVBPWM) is proposed, which has similar capacitor voltage balance characteristics as VSVPWM. The characteristic of FRCVBPWM is that there are respectively zero, N − 1 and N − 2 switching actions for the three phases of the DCMLI. Therefore, the total switching actions are greatly decreased compared with VSVPWM. The switching loss comparison between FRCVBPWM and VSVPWM is conducted by comprehensive simulations. Finally, the feasibility and superiority of FRCVBPWM over VSVPWM is verified by experiments.

1. Introduction

Recently, power electronic technology has rapidly developed in large capacity and low loss applications. The diode clamped multilevel inverter (DCMLI) was proposed [1,2], due to the advantages of lower output voltage distortion, lower electromagnetic interference and lower voltage stress [3]. This topology has received much attention and is widely used in the fields of new energy power generation, motor drives, and power quality and compensation [4,5]. Among DCMLIs, the diode clamped three-level inverter, also known as a neutral point clamped three-level inverter (NPC TLI), has been widely applied.

Capacitor voltage balance is a key issue for the DCMLI’s safe and stable operation. For an NPC TLI, some PWM strategies have been suggested for capacitor voltage control, where the carrier-based PWM (CBPWM) and space vector PWM (SVPWM) [6,7,8,9] are the two important types. It is revealed in literatures [10,11] that the relationship between a CBPWM and an SVPWM is essentially equivalent, since SVPWM can be achieved by injecting a specific zero-sequence voltage into the modulation wave of the CBPWM. However, the disadvantage of all the above methods is the low frequency oscillation on the capacitor voltage under high modulation index (MI) and low power factor (PF) operating conditions.

When the level number of the DCMLI is more than three, there are few PWM strategies for capacitor voltage control. Based on the predictive current control, an approach for a five-level DCMLI is presented [12,13], which can control both the output current and capacitor voltage. In [14,15], the passive front-end capacitor voltage balance control for a DCMLI is proposed. In [16,17], the SVPWM modulation strategy for a DCMLI is studied, but there is a problem of capacitor voltage fluctuation. For a five-level DCMLI, improved PWM strategies or an additional capacitor voltage control circuit can be adopted to control the capacitor voltage balance [18,19]. However, the increased complexity and cost of the system are the main drawbacks when applying an additional capacitor voltage control circuit.

To achieve capacitor voltage balance over the full range of the PF and the MI, a virtual SVPWM (VSVPWM) strategy is proposed [20]. This modulation strategy exhibits excellent characteristics in capacitor voltage balance control. An improved VSVPWM was presented in [21,22] to meet the other requirements of the system, such as low switching loss and reduced common-mode voltage. In addition, VSVPWM can be extended from three-phase three-level to N-level [23]; the total number of switching actions is 3N − 5. Compared to CBPWM and SVPWM, VSVPWM has the disadvantage of large switching losses, especially when the PF is low.

A PWM strategy for a DCMLI that achieves the same goals as VSVPWM, but overcomes the shortcoming of VSVPWM, is presented in this paper. Under this strategy, the full range capacitor voltage balance control can be realized. It is called a full range capacitor voltage balance PWM (FRCVBPWM), which is characterized by one phase without switching action, one phase with N − 1 switching actions, and one phase with N − 2 switching actions. In total, there are 2N − 3 switching actions for the three phases, which significantly reduce the switching losses compared to VSVPWM.

2. DCMLI and its Modulation Model

2.1. DCMLI

The topology of an N-level DCMLI is shown in Figure 1. There are 2N – switching devices with an anti-parallel diode and 2N – 4 clamping diodes in each phase. The capacitors C₁ to C_N–1 divide the DC side voltage equally when the capacitor voltage maintains balance, i.e., U_c1 = ... = U_cn–1 = 2u_dc/(N − 1). Level N − 1 is defined as when switches S₁ – S_{N – 1} are turned on and the DCMLI’s output voltage is u_dc; Level N − 2 is defined as when switches S₂ – S_N are turned on and the output voltage is u_dc× (N − 3)/(N − 1), etc. Level 0 is defined as when switches S_N – S_{2N − 2} are turned on and the output voltage is −u_dc. Hereafter, u_dc = 1 is assumed for simplicity and the positive current direction is considered as flowing from the inverter to the load. The normalized three-phase output voltages u_a, u_b and u_c can be expressed as:

$$\{\begin{array}{l}{u}_a=m\cos \omega t\\ u_b=m\cos (\omega t-2\mathsf{\pi }/3)\\ u_c=m\cos (\omega t-4\mathsf{\pi }/3)\end{array}$$

(1)

where, m ∊ [0, 1.1547] stands for the MI and ωt stands for the phase angle of phase A. The three-phase currents i_a, i_b and i_c can be expressed as:

$$\{\begin{array}{l}{i}_a=I_m\cos (\omega t-\phi )\\ i_b=I_m\cos (\omega t-2\mathsf{\pi }/3-\phi )\\ i_c=I_m\cos (\omega t-4\mathsf{\pi }/3-\phi )\end{array}$$

(2)

where, I_m stands for the peak value of the phase current and φ ∊ [0, 2π] stands for the PF angle of the load.

2.2. The PWM Model for DCMLI

The three-phase voltages given by (1) can be rearranged as:

$$\{\begin{array}{l}{u}_{\max }=\max (u_{\mathrm{a}},u_{\mathrm{b}},u_{\mathrm{c}})\\ u_{\mathrm{mid}}=\mathrm{mid}(u_{\mathrm{a}},u_{\mathrm{b}},u_{\mathrm{c}})\\ u_{\min }=\min (u_{\mathrm{a}},u_{\mathrm{b}},u_{\mathrm{c}})\end{array}$$

(3)

where, the maximum, middle and minimum phase voltages are denoted as u_max, u_mid and u_min, respectively. The phase currents corresponding to u_max, u_mid and u_min are denoted as i_max, i_mid and i_min, respectively. The general modulation model of the DCMLI, based on volt-second equilibrium is give as follows:

$$\mathbf{Gd} =\mathbf{H},$$

(4)

where,

$$\mathbf{G}={\left[\begin{array}{ccccccccc}(N-1)& \cdots & 0& -(N-1)& \cdots & 0& 0& \cdots & 0\\ 0& \cdots & 0& (N-1)& \cdots & 0& -(N-1)& \cdots & 0\\ 1& \cdots & 1& 0& \cdots & 0& 0& \cdots & 0\\ 0& \cdots & 0& 1& \cdots & 1& 0& \cdots & 0\\ 0& \cdots & 0& 0& \cdots & 0& 1& \cdots & 1\end{array}\right]}_{5\times 3N}$$

(5)

$\mathbf{d}={[d_{\max ,\mathrm{N}-1},\cdots ,d_{\max ,0},d_{\mathrm{mid},\mathrm{N}-1},d_{\mathrm{mid},0},d_{\min ,\mathrm{N}-1},\cdots ,d_{\min ,0}]}^T$, and $\mathbf{H}={\left[u_{\max }-u_{\mathrm{mid}},u_{\mathrm{mid}}-u_{\min },1,1,1\right]}^T$. The term d_kn is the duty ratio of level n of phase k (k = max, min, mid and n = 0, 1, …, N − 1). From (4), it can be seen that the relationship between the outputted line-to-line voltages and the duty ratios is revealed by the first two equations and the sum of all duty ratios of each phase must be equal to one, which is revealed by the latter three equations. The restrictive condition of d_kn can be expressed as:

$$0\le d_{kn}\le 1.$$

(6)

A specific modulation strategy can be determined by solving for the unknowns d_kn given by (4). According to (4), the number of unknowns d_kn is 3N but there are only five equations, therefore the specific solution of d_kn cannot be obtained. For the purpose of the specific solution of d_kn, additional restrictive conditions are required. In one switching cycle, the three-phase currents are assumed to be constant. To maintain each capacitor voltage balance in one switching cycle, the sum of the currents injected into each capacitor should be zero. The mathematical expression is written as:

$$i_{\max }{d}_{\max ,\mathrm{n}}+i_{\mathrm{mid}}{d}_{\mathrm{mid},\mathrm{n}}+i_{\min }{d}_{\min ,\mathrm{n}}=0\hspace{0.17em}\hspace{0.17em}(n=1,\cdots ,\mathrm{N}-2),$$

(7)

Combining (4) with (6), the capacitor voltage balance model for the DCMLI can be further obtained. Although there are N − 2 equations based on (6), the specific solution of all duty ratios cannot be obtained, and the additional restrictive conditions are still required.

2.3. Review of VSVPWM for DCMLI

Since i_a + i_b + i_c = 0 is always satisfied with the star-connected load, the simplest solution for (6) is:

$$d_{\max ,\mathrm{n}}=d_{\mathrm{mid},\mathrm{n}}=d_{\min ,\mathrm{n}}\hspace{0.17em}(n=1,\cdots ,\mathrm{N}-2),$$

(8)

assuming that:

$$d_{\mathrm{k},1}=\cdots =d_{\mathrm{k},N-2}\hspace{0.17em}(k=\max , \min , \mathrm{mid}).$$

(9)

The characteristics of VSVPWM can be described as follows. The phase corresponding to u_max has the switching sequence composed of levels 1,…, N − 1; the phase corresponding to u_min has the switching sequence composed of levels 0,…, N − 2; and the phase corresponding to u_mid has the switching sequence composed of levels 0,…, N − 1. According to the above characteristics, (9) can be obtained:

$$d_{\max ,0}=d_{\min ,N-1}=0.$$

(10)

A complete calculation model of VSVPWM for a DCMLI can be acquired by combining (4), (8), (9) and (10), and the specific solution of all duty ratios is obtained as following:

$$\begin{array}{l}\{\begin{array}{l}{d}_{\max ,0}=0\\ d_{\max ,1}=\cdots =d_{\max ,N-2}=\frac{(N-1)-u_{\max }+u_{\min }}{(N-2)(N-1)}\\ d_{\max ,N-1}=\frac{u_{\max }-u_{\min }}{(N-1)}\end{array}\\ \{\begin{array}{l}{d}_{\mathrm{mid},0}=\frac{u_{\max }-u_{\mathrm{mid}}}{(N-1)}\\ d_{\mathrm{mid},1}=\cdots =d_{\mathrm{mid},N-2}=\frac{(N-1)-u_{\max }+u_{\min }}{(N-2)(N-1)}\\ d_{\mathrm{mid},N-1}=\frac{u_{\mathrm{mid}}-u_{\min }}{(N-1)}\end{array}\\ \{\begin{array}{l}{d}_{\min ,0}=\frac{u_{\max }-u_{\min }}{(N-1)}\\ d_{\min ,1}=\cdots =d_{\min ,N-2}=\frac{(N-1)-u_{\max }+u_{\min }}{(N-2)(N-1)}\\ d_{\min ,N-1}=0\hspace{0.17em}\end{array}\end{array}$$

(11)

The following conclusion can be obtained from (11). (i) All duty ratios are independent of the phase currents. (ii) When m ∊ [0, 1.1547], (5) is satisfied for all duty ratios. (iii) The condition for maintaining the voltage balance of each capacitor in one switching cycle given by (6) is satisfied. Although VSVPWM exhibits excellent capacitor voltage balance performance over the full range of PFs and MIs, the total of 3N − 5 switching actions results in large switching losses, which is a major drawback.

3. The Proposed FRCVBPWM for DCMLI

3.1. The Proposed FRCVBPWM

In this paper, FRCVBPWM is proposed to solve the problem of the large switching losses of VSVPWM. Assume that one phase has no switching action, one phase has N − 1 switching actions, and one phase has N − 2 switching actions; then there are only 2N – 3 switching actions for the three phases in one switching cycle. This is the basic idea for FRCVBPWM proposed in this paper. There are four cases, as listed in

Table 1. The switching number under different modes of full range capacitor voltage balance PWM (FRCVBPWM).

MAX_PB/MID_N − 1/MIN_N − 2		MAX_PB/MIN_N − 1/MID_N − 2	MIN_NB/MAX_N − 1/MID_N − 2	MIN_NB/MID_N − 1/MAX_N − 2
umax	0	0	N − 1	N − 2
umid	N − 1	N − 2	N − 2	N − 1
umin	N − 2	N − 1	0	0

.

3.2. The Duty Ratio Calculation under Different Modes in One Switching Cycle

(a). Mode 1: MAX_PB/MID_N – 1/MIN_N – 2

In this mode, the phase corresponding to u_max is clamped to level N − 1 (i.e., positive bus) without a switching action. Therefore, the duty ratios with respect to u_max are written as

$$d_{\max ,N-1}=1,\hspace{0.17em}{d}_{\max ,N-2}\cdots =d_{\max ,0}=0.$$

(12)

For u_mid, the switching sequence is composed of levels 0,..., N − 1 and there are N − 1 switching actions; for u_min, the switching sequence is composed of levels 0,..., N − 2 and there are N − 2 switching actions. Since there is no level N − 1 in the switching sequence for u_min, d_{min,N − 1} is determined as:

$$d_{\min ,N-1}=0.$$

(13)

Thus, (7) is rewritten as:

$$i_{\mathrm{mid}}{d}_{\mathrm{mid},\mathrm{n}}+i_{\min }{d}_{\min ,\mathrm{n}}=0\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}(\mathrm{n}=1,2,\cdots ,N-2),$$

(14)

Letting $d_{\mathrm{mid},\mathrm{n}}=d_{\mathrm{mid},1}\hspace{0.17em},\hspace{0.17em}{d}_{\min ,\mathrm{n}}=d_{\min ,1}\hspace{0.17em}(n=2,\cdots ,N-2)$ and $-i_{\mathrm{mid}}/i_{\min }=K$, so:

$$K{d}_{\mathrm{mid},1}=\cdots =K{d}_{\mathrm{mid},N-2}=d_{\min ,1}=\cdots =d_{\min ,N-2}.$$

(15)

Therefore, the calculation model of FRCVBPWM for the DCMLI can be acquired by combining (4), (12)–(15), and the specific solution of all duty ratios is listed in

Table 2. All duty ratios under different modes of FRCVBPWM.

Mode	Duty Ratio	Mode	Duty Ratio
Mode 1: MAX_PB/MID_N − 1/MIN_N − 2	$\begin{array}{l}{d}_{\min ,0}=1-2\frac{(N-1)-u_{L1}}{(N-1)}\\ d_{\min ,N-2}=\dots =d_{\min ,1}=2\frac{(N-1)-u_{L1}}{(N-2)(N-1)}\\ d_{\min ,N-1}=0\\ d_{\mathrm{mid},0}=\frac{u_{L2}}{N-1}+\frac{u_{L1}-(N-1)}{K(N-1)}\\ d_{\mathrm{mid},N-2}=\dots =d_{\mathrm{mid},1}=\frac{2}{K}\frac{(N-1)-u_{L1}}{(N-2)(N-1)}\\ d_{\mathrm{mid},N-1}=1-\frac{u_{L2}}{N-1}-\frac{(N-1)-u_{L1}}{K(N-1)}\\ d_{\max ,N-1}=1,d_{\max ,N-2}=\dots =d_{\max ,1}=0,d_{\max ,0}=0\\ K=-i_{\mathrm{mid}}/i_{\min }\end{array}$	Mode 2-1: MAX_PB/MIN_N − 1/MID_N − 2 (The output sequence of the phase corresponding to umid is composed of levels 1... , N − 1)	$\begin{array}{l}{d}_{\min ,0}=\frac{u_{L1}-K{u}_{L2}}{(N-1)}\\ d_{\min ,N-2}=\cdots =d_{\min ,1}=\frac{2K{u}_{L2}}{(N-1)(N-2)}\\ d_{\min ,N-1}=1-\frac{u_{L1}+K{u}_{L2}}{(N-1)}\\ d_{\mathrm{mid},0}=0\\ d_{\mathrm{mid},N-2}=\cdots =d_{\mathrm{mid},1}=\frac{2u_{L2}}{(N-1)(N-2)}\\ d_{\mathrm{mid},N-1}=1-\frac{2u_{L2}}{(N-1)}\\ d_{\max ,N-1}=1,d_{\max ,N-2}=\cdots =d_{\max ,1}=0,d_{\max ,0}=0\\ K=-i_{\mathrm{mid}}/i_{\min }\end{array}$
Mode 2-2: MAX_PB/MIN_N − 1/MID_N − 2 (The output sequence of the phase corresponding to umid is composed of levels 0..., N − 2)	$\begin{array}{l}{d}_{\min ,0}=\frac{u_{L1}+K{u}_{L2}}{N-1}-K\\ d_{\min ,N-2}=\cdots =d_{\min ,1}=\frac{2K\left[\left(N-1\right)-u_{L2}\right]}{\left(N-2\right)\left(N-1\right)}\\ d_{\min ,N-1}=\frac{u_{L1}}{1-N}+\frac{K{u}_{L2}}{N-1}+1-K\\ d_{\mathrm{mid},0}=-1+2\frac{u_{L2}}{\left(N-1\right)}\\ d_{\mathrm{mid},N-2}=\cdots =d_{\mathrm{mid},1}=\frac{2\left[\left(N-1\right)-u_{L2}\right]}{\left(N-2\right)\left(N-1\right)}\\ d_{\mathrm{mid},N-1}=0\\ d_{\max ,N-1}=1,d_{\max ,N-2}=\dots =d_{\max ,1}=0,d_{\max ,0}=0\\ K=-i_{\mathrm{mid}}/i_{\min }\end{array}$	Mode 3-1: MIN_NB/MAX_N − 1/MID_N − 2 (The output sequence of the phase corresponding to umid is composed of levels 1..., N − 1)	$\begin{array}{l}{d}_{\min ,0}=1,d_{\min ,N-2}=\cdots =d_{\min ,1}=0,d_{\min ,N-1}=0\\ d_{\mathrm{mid},0}=0\\ d_{\mathrm{mid},N-2}=\cdots =d_{\mathrm{mid},1}=2\frac{(N-1)-u_{L3}}{(N-1)(N-2)}\\ d_{\mathrm{mid},N-1}=\frac{2u_{L3}}{(N-1)}-1\\ d_{\max ,0}=1-\frac{u_{L1}}{N-1}+\frac{K{u}_{L3}}{(N-1)}-K\\ d_{\max ,N-2}=\cdots =d_{\max ,1}=2K\frac{(N-1)-u_{L3}}{(N-1)(N-2)}\\ d_{\max ,N-1}=-K\frac{(N-1)-u_{L3}}{(N-1)}+\frac{u_{L1}}{N-1}\\ K=-i_{\mathrm{mid}}/i_{\max }\end{array}$
Mode 3-2: MIN_NB/MAX_N − 1/MID_N − 2 (The output sequence of the phase corresponding to umid is composed of levels 0..., N − 2)	$\begin{array}{l}{d}_{\min ,0}=1,d_{\min ,N-2}=\cdots =d_{\min ,1}=0,d_{\min ,N-1}=0\\ d_{\mathrm{mid},0}=1-\frac{2u_{L3}}{(N-1)}\\ d_{\mathrm{mid},N-2}=\cdots =d_{\mathrm{mid},1}=\frac{2u_{L3}}{(N-1)(N-2)}\\ d_{\mathrm{mid},N-1}=0\\ d_{\max ,0}=1-\frac{u_{L1}+K{u}_{L3}}{(N-1)}\\ d_{\max ,N-2}=\cdots =d_{\max ,1}=\frac{2K{u}_{L3}}{(N-1)(N-2)}\\ d_{\max ,N-1}=\frac{u_{L1}-K{u}_{L3}}{(N-1)}\\ K=-i_{\mathrm{mid}}/i_{\max }\end{array}$	Mode 4: MIN_NB/MID_N − 1/MAX_N − 2	$\begin{array}{l}{d}_{\min ,0}=1,d_{\min ,N-2}=\cdots =d_{\min ,1}=0,d_{\min ,N-1}=0\\ d_{\mathrm{mid},0}=1-\frac{1}{K}\left[1-\frac{u_{L1}}{(N-1)}\right]-\frac{u_{L2}}{N-1}\\ d_{\mathrm{mid},N-2}=\cdots =d_{\mathrm{mid},1}=\frac{1}{K}\left[\frac{2}{(N-2)}-\frac{2u_{L1}}{(N-1)(N-2)}\right]\\ d_{\mathrm{mid},N-1}=\frac{u_{L2}}{N-1}-\frac{1}{K}\left[1-\frac{u_{L1}}{(N-1)}\right]\\ d_{\max ,0}=0\\ d_{\max ,N-2}=\cdots =d_{\max ,1}=\frac{2}{(N-2)}-\frac{2u_{L1}}{(N-1)(N-2)}\\ d_{\max ,N-1}=\frac{2u_{L1}}{(N-1)}-1\\ K=-i_{\mathrm{mid}}/i_{\max }\end{array}$

Remark: $u_{\max }-u_{\min }=u_{L1},u_{\max }-u_{\mathrm{mid}}=u_{L2},u_{\mathrm{mid}}-u_{\min }=u_{L3}$.

.

(b). Mode 2: MAX_PB/MIN_N − 1/MID_N − 2

In this mode, the phase corresponding to u_max is clamped to level N − 1 without a switching action. For u_min, the switching sequence is composed of levels 0,..., N − 1 and there are N − 1 switching actions. For u_mid, there are N − 2 switching actions. There are two cases for the switching sequence of u_mid:

Mode 2-1: the switching sequence of u_mid is composed of levels 1..., N − 1.

Mode 2-2: the switching sequence of u_mid is composed of levels 0..., N − 2.

(c). Mode 3: MIN_NB/MAX_N − 1/MID_N − 2

In this mode, the phase corresponding to u_min is clamped to level 0 (i.e., negative bus) without a switching action. For u_max, the switching sequence is composed of levels 0,..., N − 1 and there are N − 1 switching actions. For u_mid, there are N − 2 switching actions. It also has two cases for the switching sequence of u_mid:

Mode 3-1: the switching sequence of u_mid is composed of levels 1..., N − 1.

Mode 3-2: the switching sequence of u_mid is composed of levels 0 ..., N − 2.

(d). Mode 4: MIN_NB/MID_N − 1/MAX_N − 2

In this mode, the phase corresponding to u_min is clamped to level 0 without a switching action. For u_mid, the switching sequence is composed of levels 0,..., N − 1 and there are N − 1 switching actions. For u_max, the switching sequence is composed of levels 1,..., N − 1 and there are N − 2 switching actions.

The switching sequences of the three phases under different modes are presented in Figure 2. The calculation models of all duty ratios for FRCVBPWM under different modes are presented in Table 2. It can be noted that the duty ratios under different modes are determined by the three-phase voltages and currents. The mode is available if the calculated duty ratios under this mode satisfy (6). The application area of one mode means that the mode is available within the area. The application areas under several certain φ under different modes are shown in Figure 3, Figure 4, Figure 5 and Figure 6, where the white areas stand for the application areas.

4. Selecting the Mode Based on the Switching Loss

It can be seen from Figure 3, Figure 4, Figure 5 and Figure 6 that there is at least one available mode in any condition of m and ωt, and there are even three available modes in some conditions of m and ωt, so an optimal available mode can be chosen. In this paper, the minimum switching loss is used as the selection criterion. The switching loss evaluation function for different modes can be expressed as:

$$P_{SL}={\displaystyle \sum _{k=\max ,\min ,mid}\left|i_k\right|\times f_k},$$

(16)

where f_k represents the switching action number of phase k.

Based on (16), the selected modes with several certain values of φ under the whole range of m and ωt are shown in Figure 7. While φ = 0, it is necessary to switch between modes 1, 2-2, 3-1 and 4 when m is greater than 1 and it is only necessary to switch between modes 2-2 and 3-1 when m is less than 1. While φ = π/2, it is necessary to switch between modes 2-2 and 3-1 when m is about less than 0.577 and it is necessary to switch between modes 1 and 4 when m is about greater than 0.577.

5. The Implementation of FRCVBPWM

A carrier-based PWM method generates the PWM sequences by comparing the carrier with the modulation wave. This method is used for the implementation of FRCVBPWM because it can be easily carried out. For a multilevel inverter, multiple modulation waves are required, which can be obtained based on geometric relationships:

$$\{\begin{array}{l}{u}_{k,N-1}=d_{k,N-1}{u}_{dc}\\ u_{k,N-2}=(d_{k,N-1}+d_{k,N-2})u_{dc}\\ u_{k,N-3}=(d_{k,N-1}+d_{k,N-2}+d_{k,N-3})u_{dc}\\ ⋮\\ u_{k,1}=(d_{k,N-1}+\cdots +d_{k,1})u_{dc}\end{array}.$$

(17)

Multiple PWM sequences can be acquired by comparing a single carrier with multiple modulation waves; then, the final PWM sequence of the FRCVBPWM can be realized by adding the acquired multiple PWM sequences, as shown in Figure 8. The switching action number of FRCVBPWM and VSVPWM under different levels is shown in

Table 3. The switching action number of FRCVBPWM and VSVPWM.

	Three-Level	Five-Level	...-Level	N-Level
FRCVBPWM	3	7	...	2N − 3
VSVPWM	4	10	...	3N − 5

.

6. Switching Loss Analysis

For different modulation strategies, the conduction losses are generally considered to be equal and are not taken into account. Therefore, the loss analysis mainly focuses on switching losses. The average switching losses in a fundamental period can be calculated using the method proposed in [24], which is adopted here. When the phase current peaks are the same, the average switching losses of FRCVBPWM and VSVPWM with the variation of φ and m can be calculated, which are recorded as P_{SL_FCVB} and P_{SL_VSV}, respectively.

Figure 9 shows the ratios of P_{SL_FCVB} to P_{SL_VSV} for a DCMLI with different levels. It can be seen that in the operating range of the higher m and lower PF, the switching losses of FRCVBPWM are significantly lower than that of VSVPWM. In addition, the ratios of P_{SL_FCVB} to P_{SL_VSV} are reduced more obviously with the increase of levels.

7. Experimental Verification

A three-level DCMLI is built to verify the proposed FRCVBPWM. The DSP used as the main controller chip is Freescale’s MC56F84789, and the IGBT model used as the switching device is F3L300R07PE4. The experimental parameters are listed in

Table 4. Experimental parameters.

Parameter	Value
DC side voltage	200 V
Upper and lower capacitance values	1000 μF
Load factor with high PF 1 (ZH1)	2ejπ/12 Ω
Load factor with high PF 2 (ZH2)	6ejπ/12 Ω
Load factor with low PF 1 (ZL1)	2ej5π/12 Ω
Load factor with low PF 2 (ZL2)	6ej5π/12 Ω
Fundamental frequency	50 Hz

.

The steady-state experimental results under four conditions with different m and φ for FRCVBPWM and VSVPWM are shown in Figure 10 and Figure 11, respectively. The capacitor voltage can be controlled effectively under the two modulation strategies.

From the waveform of phase voltage u_a shown in Figure 10, it can be seen that there is about one-third of an interval of a fundamental cycle in which it outputs levels 0, 1 and 2. It indicates that there are two switching actions during this interval, and there is one switching action during the other interval. From the waveform of phase voltage u_a shown in Figure 11, it can be noted that there is a clamping interval in which the phase voltage u_a is clamped to the positive or negative bus. Moreover, the interval with two switching actions is roughly equal to the clamping interval. Thus, each phase has one switching action on average, which reduces the switching losses of FRCVBPWM.

For FRCVBPWM and VSVPWM, the switching loss comparisons under four conditions are shown in Figure 12. When PF is higher, the switching loss difference between FRCVBPWM and VSVPWM is very small. When PF is lower, the switching losses of VSVPWM are significantly greater than that of FRCVBPWM.

When m = 0.3, the three-phase voltage for FRCVBPWM and VSVPWM in one fundamental period are shown in Figure 13. Under VSVPWM, the switching sequence of one phase is composed of levels 0, 1 and 2, and the other two phases are composed of two levels. Thus, there are in total four switching actions for the three phases in one switching cycle. Under FRCVBPWM, the switching sequence of one phase is composed of levels 0, 1 and 2, and one phase is composed of two levels, and one phase is clamped. Thus, there are in total three switching actions for the three phases in one switching cycle.

The dynamic experimental results of the proposed FRCVBPWM are presented in Figure 14, including a sudden change of m and load, respectively. From the dynamic experimental results, it can be seen that not only is DC offset, but also an AC ripple does not appear on the capacitor voltage. Therefore, the proposed FRCVBPWM has excellent capacitor voltage control performance both in steady state and dynamic process.

8. Conclusions

Because one phase is clamped, the switching action number of the proposed FRCVBPWM is reduced from 3N − 5 to 2N − 3 compared to VSVPWM for DCMLI applications, which greatly reduces switching loss. However, the full range capacitor voltage balance can be effectively achieved for FRCVBPWM, just like VSVPWM. Therefore, it can be concluded that the proposed FRCVBPWM has significant advantages in balancing capacitor voltage and reducing switching loss.