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Fast Multibit Decision Polar Decoder for Successive-Cancellation List Decoding

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Abstract

Successive-cancellation list (SCL) decoding for polar codes has the disadvantage of high latency owing to serial operations. To improve the latency, several algorithms with additional circuits have been proposed, but the area becomes larger. This paper proposes a fast multibit decision method having-high area efficiency based on the SCL decoding algorithm. First, multiple bits can be determined to reduce clock cycles using new nodes represented by the information bits and frozen bits. We propose the new nodes called the combined nodes and the other node in this paper. The combined nodes that combine redundant operations of the fast-simplified SC (fast-SSC) algorithm can increase area efficiency. The other node with bit patterns other than the node types of the fast-SSC algorithm performs an 8-bit multibit decision to reduce the number of decoding cycles. Latency is further reduced by applying a sphere decoding method to the other node. In addition, a sorter is proposed to reduce the critical path delay. As a large number of path metrics causes sorter delays, the proposed sorter can achieve high throughput with the small area. The proposed (1024, 512) SCL decoder showed negligible performance degradation in the simulation using Matlab and was synthesized using 65 nm CMOS technology. The proposed decoder achieves about 1.3Gbps with the small area. As a result, the area-throughput efficiency is at least 1.4 times higher than the state-of-the-art works over 1 Gbps.

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References

  1. Arıkan, E. (2009). Channel polarization: A method for constructing capacity achieving codes for symmetric binary-input memoryless channels. IEEE Transactions on Information Theory, 55(7), 3051–3073.

    Article  MathSciNet  Google Scholar 

  2. Alamdar-Yazdi, A., & Kschischang, F. R. (2011). A simplified successive-cancellation decoder for polar codes. IEEE Communications Letters, 15(12), 1378–1380.

    Article  Google Scholar 

  3. Sarkis, G., Giard, P., Vardy, A., Thibeault, C., & Gross, W. J. (2014). Fast polar decoders: Algorithm and implementation. IEEE Journal on Selected Areas in Communications, 32(5), 946–957.

    Article  Google Scholar 

  4. Giard, P., Balatsoukas-Stimming, A., Sarkis, G., Thibeault, C., & Gross, W. J. (2016). Fast low-complexity decoders for low-rate polar codes. J. Signal Process. Syst., 1–11.

  5. M. Hanif and M. Ardakani, “Fast successive-cancellation decoding of polar codes: identification and decoding of new nodes,” IEEE Commun. Lett., vol. PP, no. 99, 2017.

  6. A. Pamuk and E. Arikan (2013) “A two phase successive cancellation decoder architecture for polar codes,” in Proc. IEEE ISIT, pp. 957–961.

  7. Yuan, B., & Parhi, K. K. (Apr. 2014). Low-latency successive-cancellation polar decoder architectures using 2-bit decoding. IEEE Trans. Circuits Syst. I, Reg. Papers, 61(4), 1241–1254.

    Article  Google Scholar 

  8. Raymond, A., & Gross, W. (Oct. 2014). A scalable successive-cancellation decoder for polar codes. IEEE Transactions on Signal Processing, 62(20), 5339–5347.

    Article  MathSciNet  Google Scholar 

  9. A. Mishra, A. J. Raymond, L. Amaru, G. Sarkis, C. Leroux, P. Meinerzhagen, A. Burg, and W. J. Gross (2012) “A successive cancellation decoder ASIC for a 1024-bit polar code in 180 nm CMOS,” in Proc. IEEE Asian Solid State Circuits Conf. (A-SSCC), pp. 205–208.

  10. C. Leroux, I. Tal, A. Vardy, and W. J. Gross (2011) “Hardware architectures for successive cancellation decoding of polar codes,” in Proc. IEEE Conf. Int. Acoust., Speech, Signal Process. (ICASSP), pp. 1665–1668.

  11. Leroux, C., Raymond, A., Sarkis, G., & Gross, W. (2013). A semi-parallel successive-cancellation decoder for polar codes. IEEE Transactions on Signal Processing, 61(2), 289–299.

    Article  MathSciNet  Google Scholar 

  12. Zhang, C., & Parhi, K. K. (2014). Latency analysis and architecture Design of Simplified SC polar decoders. IEEE Trans. Circuits and Systems-II: Transactions Briefs, 61(2), 115–119.

    Article  Google Scholar 

  13. Tal, I., & Vardy, A. (May 2015). List decoding of polar codes. IEEE Transactions on Information Theory, 61(5), 2213–2226.

    Article  MathSciNet  Google Scholar 

  14. Balatsoukas-Stimming, A., Bastani Parizi, M., & Burg, A. (2015). LLR-based successive cancellation list decoding of polar codes. IEEE Transactions on Signal Processing, 63(19), 5165–5179.

    Article  MathSciNet  Google Scholar 

  15. Xiong, C., Lin, J., & Yan, Z. (2016). Symbol-decision successive cancellation list decoder for polar codes. IEEE Transactions on Signal Processing, 64(3), 675–687.

    Article  MathSciNet  Google Scholar 

  16. Yuan, B., & Parhi, K. K. (Jan. 2017). LLR-based successive-cancellation list decoder for polar codes with multibit decision. IEEE Trans. Circuits Syst. II, 64(1), 21–25.

    Article  Google Scholar 

  17. S. A. Hashemi, C. Condo, and W. J. Gross (2017) “Fast simplified successive-cancellation list decoding of polar codes,” in IEEE Wireless Commun. and Netw. Conf., pp. 1–6.

  18. Hashemi, S. A., Condo, C., & Gross, W. J. (Dec. 2016). A fast polar code list decoder architecture based on sphere decoding. IEEE Trans. Circuits Syst. I, 63(12), 2368–2380.

    Article  Google Scholar 

  19. Hashemi, S. A., Condo, C., & Gross, W. J. (2017). Fast and flexible successive-cancellation list decoders for polar codes. IEEE Transactions on Signal Processing, 65(21), 5756–5769.

    Article  MathSciNet  Google Scholar 

  20. Lin, J., Xiong, C., & Yan, Z. (2016). A high throughput list decoder architecture for polar codes. IEEE Trans. Very Large Scale Integr. Syst., 24(6), 2378–2391.

    Google Scholar 

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Acknowledgments

This work was supported by the Ministry of Science, ICT, and Future Planning, Korea, under the Information Technology Research Center support program (IITP-2018-2016-0-00309-002) supervised by the Institute for Information & Communications Technology Promotion and the National Research Foundation of Korea by the Korea government (NRF-2017R1A2A2A05001046).

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  1. Ajou University Suwon, Suwon-si, Gyeonggi-do, South Korea

    Seo Lin Jeong, Jung Hyun Bae & Myung Hoon Sunwoo

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  1. Seo Lin Jeong
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  2. Jung Hyun Bae
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  3. Myung Hoon Sunwoo
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Correspondence to Myung Hoon Sunwoo.

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Jeong, S.L., Bae, J.H. & Sunwoo, M.H. Fast Multibit Decision Polar Decoder for Successive-Cancellation List Decoding. J Sign Process Syst 93, 127–136 (2021). https://doi.org/10.1007/s11265-020-01570-x

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