Abstract
A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead.
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References
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Acknowledgements
Authors would like to thank Ministry of Electronics and Information Technology (MeitY), Government of India, for providing EDA tools through SMDP-VLSI Project.
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Bhat, K.G., Laxminidhi, T. & Bhat, M.S. Resolution-independent fully differential SCI-based SAR ADC architecture using six unit capacitors. Sādhanā 45, 184 (2020). https://doi.org/10.1007/s12046-020-01421-2
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DOI: https://doi.org/10.1007/s12046-020-01421-2