A 40 μW–30 mW generated power, 280 Ω–1.68 kΩ load resistance CMOS controllable constant-power source for thermally-based sensor applications

Abstract

A controllable constant-power source in 0.35 μm CMOS technology is presented in this paper. It is based on the resistive mirror method, and suitable for thermally-based sensor applications. Two versions have been developed and fabricated: a high-voltage design with a single supply of 10 V, and a low-voltage design with a single supply of 3.6 V. The measured results for the high voltage (low voltage) design are the following: a generated power dynamic range of 57.5 dB (52.4 dB), a load resistance dynamic range of 15.6 dB (12 dB), a voltage efficiency of 0.7 (0.61), and a relative error of the generated power less than 1.8% (1.8%). The temperature compensation of the controllable constant-power source has been performed for the temperature range 0 °C ≤ T ≤ 50 °C. The stability test has been carried out using a resistive load in pulse mode operation confirming that the stability of the proposed controllable constant-power source is not dependent on either the load resistance or the generated power.

1 Introduction

Controllable constant-power sources (CCPSs) generate a controllable constant power independently of load resistance variations within predefined limits. The predefined limits are referred to the smallest and the largest generated powers P_Lmin and P_Lmax, respectively, which can be dissipated in the variable resistive load with the largest and the smallest load resistances R_Lmax and R_Lmin, respectively, and with the largest allowed deviation from the nominal value of the generated power P_L. In addition, the voltage efficiency (the ratio of the overall voltage range across the resistive load R_L and the supply voltage) should be as large as possible. A constant-power dissipation of the CCPS applied as an interface of the thermal-based sensor surrounded by a gas or liquid fluid is used for measurements of the volumetric flow rate and the point velocity of a fluid [1, 2].

Depending on the design and the technology used, existing CCPSs can be classified as follows. The CCPS based on the BJT translinear loop [3,4,5], applied in plant water status measurements, seepage meters, and very slow downward flow rate meters, respectively, provides a large generated power dynamic range of P_Lmax/P_Lmin = 1000. It exhibits superior performances compared to the CCPS based on the CMOS translinear loop [6, 7], the later used in gas monitoring. Commercially available BiCMOS power monitors are the basis for the CCPSs [8, 9], the later used in flow rate measurements, achieve a large load resistance dynamic range of R_Lmax/R_Lmin = 50 for a generated power up to 100 mW, with the inclusion of two supply voltage sources. The simple CMOS CCPSs [10, 11] implementing first order compensation by injecting controlled current into the resistive load are usable only for relatively small load resistance dynamic range R_Lmax/R_Lmin, with an error of the generated power of 11% for a load variation of 100% in [10]. A switching technique applied in the CCPS [12] is based on an adjustment of a switching duty cycle of the primary coil of the transformer by a power switch controller. A high frequency bandwidth up to 5 MHz of the CCPS [13] is achieved by implementing a current-mode multiplier/divider and second generation current conveyor. The resistive mirror based CCPSs [14, 15] keep the equality of the variable channel resistances of two non-saturated MOSFETs leading to a constant generated power.

Similar to [14, 15], the proposed CCPS designed in 0.35 μm CMOS technology is based on the resistive mirror method [16, 17]. The proposed CCPS has a simpler design and two operational amplifiers less than that in [14], and one operational amplifier less than that in [15]. Two operational amplifiers used in the proposed CCPS are based on a simple CMOS telescopic cascoded design, unlike in [14, 15] where discrete off-the-shelf operational amplifiers in bipolar technology with very low offset voltages have been used. In addition, the proposed CCPS has a fewer number of feedback loops than that in [14, 15], and provides better stability. The stability of the proposed CCPS is not dependent on either the load resistance or the generated power, unlike in [14] where the stability depends on both the load resistance and the generated power. The proposed design avoids the usage of any arithmetic circuit like in [15] where the subtraction of two voltages is performed using a differential amplifier with unity differential gain. The design is immune to temperature variations in the range 0 °C ≤ T ≤ 50 °C. In addition to a high-voltage (HV) design of the CCPS with a single supply of 10 V, a low-voltage (LV) design of the CCPS with a single supply of 3.6 V has been made in order to satisfy the requirements of low voltage applications and standard CMOS technologies. Both the HV CCPS and the LV CCPS have the same circuit schematics, but the type and dimensions of MOSFETs are different. The generated power dynamic range P_Lmax/P_Lmin of the proposed HV CCPS is 33.3 times larger than that in [14], and 16.2 times larger than that in [15]. The load resistance dynamic range R_Lmax/R_Lmin of the proposed HV CCPS is 2 times larger than that in [14], and 1.2 times larger than that in [15]. At the same time, the relative errors of the proposed HV CCPS are smaller than those in [14, 15]. On the other hand, the generated power dynamic range P_Lmax/P_Lmin of the proposed LV CCPS is 18.5 times larger than that in [14], and 9 times larger than that in [15]. The load resistance dynamic range R_Lmax/R_Lmin of the proposed LV CCPS is 1.33 times larger than that in [14], and 1.25 times smaller than that in [15]. At the same time, the relative errors of the proposed LV CCPS are smaller than those in [14, 15]. These results confirm that the proposed LV CCPS and especially HV CCPS have much better performances than existing CMOS CCPSs. Moreover, according to the figure of merit introduced in [15], the performances of the proposed CMOS HV CCPS are comparable with the CCPS designed in bipolar technology [3,4,5]. This is an important achievement from the technology standpoint because a cheaper CMOS technology is preferred over the bipolar technology, which is nowadays often available only as BiCMOS technology.

2 Circuit description

The simplified circuit schematic of the proposed resistive mirror based CCPS is shown in Fig. 1 (upper left). It is assumed that operational amplifiers OA₁ and OA₂ are capable of working with small input voltages. To that aim, simple source followers with p-channel MOSFTEs working as DC voltage shifters are placed at the inputs of the operational amplifiers. The resistive mirror is designed by the n-channel MOSFETs M₁ and M₂ operating in the non-saturated region. Hence, the channel resistances R_DS1 and R_DS2 of these MOSFETs are the following [18,19,20]

$$ R_{DSi} \approx \frac{1}{{\beta_{i} \left( {V_{GSi} - V_{ti} } \right)}},_{{}} i \in \left\{ {1,_{{}} 2} \right\} $$

(1)

where β_i, V_GSi, and V_ti are the transconductance parameter, gate-to-source voltage, and threshold voltage of M_i, respectively. The resistive image is presented by M₁, while the resistive original is presented by M₂. The resistive load R_L is put in the negative feedback branch of OA₁. Together with the resistive image M₁ and the reference voltage source V_REF, they make the non-inverting amplifier. The drain-to-source voltage V_DS1 of M₁ is equal to the reference voltage, V_DS1 = V_REF. To provide non-saturated operation of M₁, the reference voltage V_REF should be small enough. Unlike in [14, 15] where the resistive load current I_L and the resistive image current I_D1 are only nearly equal, in the proposed approach the same current I_L flows through the resistive load R_L and the resistive image M₁. The resistive image resistance presented by the channel resistance R_DS1 of the non-saturated M₁ is equal to

Fig. 1

Simplified (upper left) and complete circuit schematic of the proposed resistive mirror based CCPS with the dimensions (in μm) of the MOSFETs used

$$ R_{DS1} = \frac{{V_{DS1} }}{{I_{D1} }} = \frac{{V_{REF} }}{{I_{L} }} $$

(2)

The voltage V_L across the resistive load R_L, increased by the reference voltage V_REF, appears at the output of OA₁. The voltage V_L + V_REF is attenuated by the resistive voltage divider made by the resistors R₁ and R₂. The voltage V_R12 at the output of the resistive voltage divider R₁–R₂ can be expressed as

$$ V_{R12} = \frac{{R_{2} }}{{R_{1} + R_{2} }}\left( {V_{L} + V_{REF} } \right) = k_{R12} \left( {V_{L} + V_{REF} } \right) $$

(3)

where k_R12 = R₂/(R₁ + R₂) represents the magnitude of the attenuation of the resistive voltage divider R₁–R₂. The goal of the proposed approach is to achieve the equality of the drain-to-source voltage V_DS2 of M₂ and the attenuated resistive load voltage V_L: V_DS2 = k_R12V_L. For a large enough generated powers P_L, assuming a large enough load resistances R_L providing V_L ≫ V_REF, the relation (3) can be approximated as follows: V_R12 ≈ k_R12V_L. Now, it would be easy to provide V_DS2 = V_R12 ≈ k_R12V_L. However, to achieve precisely generated powers P_L directed by the fulfilment of the condition V_DS2 = k_R12V_L, the DC voltage source V_B with the voltage

$$ V_{B} = \frac{{R_{2} }}{{R_{1} + R_{2} }}V_{REF} = k_{R12} V_{REF} $$

(4)

and the polarity indicated in Fig. 1 is included. The voltage V_DS2 = k_R12V_L has to be small enough in order to provide non-saturated operation of M₂ representing the resistive original. This is why the coefficient k_R12 < 1 must be small enough. Consequently, the voltage V_B (4) is in the order of mV. The reference current source I_REF is connected to the drain of M₂. Because the drain-to-source voltage of M₂ is small enough to provide its non-saturated operation, and the supply voltage V_DD is large enough, the voltage across the reference current source I_REF is always large enough to provide its normal operation independent of the generated power P_L and/or the load resistance R_L. The resistive original resistance presented by the channel resistance R_DS2 of the non-saturated M₂ is equal to

$$ R_{DS2} = \frac{{V_{DS2} }}{{I_{D2} }} = \frac{{k_{R12} V_{L} }}{{I_{REF} }} = \frac{{R_{2} }}{{R_{1} + R_{2} }}\frac{{V_{L} }}{{I_{REF} }} $$

(5)

The resistive image resistance R_DS1 (2) is inversely proportional to the resistive load current I_L, and the resistive original resistance R_DS2 (5) is directly proportional to the resistive load voltage V_L. So, by providing proportionality between the channel resistances R_DS1 and R_DS2, R_DS1/R_DS2 = const., the power P_L = V_LI_L can be generated in the resistive load R_L independent of its resistance. To provide the proportionality between the channel resistances R_DS1 and R_DS2 (1), another two conditions for the achievement of precisely generated powers P_L should be fulfilled: the equality of the gate-to-source voltages V_GS1 = V_GS2, and the equality of the threshold voltages V_t1 = V_t2 of M₁ and M₂. In that case, the proportionality between the channel resistances R_DS1 and R_DS2 is determined by the ratio of the corresponding transconductance parameters β₁ and β₂: R_DS1/R_DS2 = β₂/β₁, (1). The equality of the gate-to-source voltages V_GS1 and V_GS2 is provided by the design itself. On the other hand, M₁ and M₂ should be well matched in order to provide the equality of their threshold voltages V_t1 and V_t2. So, the transconductance parameters β₁ and β₂ of M₁ and M₂ are equal, β₁ = β₂. The drain-to-source voltages V_DS1 = V_REF and V_DS2 = k_R12V_L of M₁ and M₂, respectively, are sufficiently small, but different, and the channel resistances R_DS1 and R_DS2 of non-saturated M₁ and M₂ can be only nearly equal [14, 15]. According to the relation (1) and because the overall negative feedback is maintained, the approximate equality of the resistive image resistance R_DS1 (2) and the resistive original resistance R_DS2 (5) is provided, R_DS1 ≈ R_DS2. This leads to the expression for the power P_L generated in the resistive load R_L

$$ P_{L} = V_{L} I_{L} \approx \frac{1}{{k_{R12} }}V_{REF} I_{REF} = \left( {1 + \frac{{R_{1} }}{{R_{2} }}} \right)V_{REF} I_{REF} $$

(6)

According to (6), the generated power P_L is independent of the load resistance R_L. The controllability of the generated constant power P_L can be performed by varying the reference voltage V_REF, and/or by varying the reference current I_REF. The model (6) has been achieved in the proposed CCPS without usage of any differential amplifier, which is the source of the errors in the CCPS [15]. Moreover, there are the systematic errors in the CCPSs [14, 15] caused by the difference between the resistive load current I_L and the resistive image current I_D1 due to the designs themselves. Because the resistive image resistance R_DS1 is inversely proportional to the resistive image current I_D1, a relatively small deviation of the resistive image current I_D1 from the resistive load current I_L could cause a quite large error of the generated power P_L in [14, 15]. To keep the resistive load current I_L and the resistive image current I_D1 nearly equal, the design [14] assumes that one of the resistances within the resistive voltage divider connected in parallel to the resistive load R_L have to be much larger (470 kΩ) than the largest load resistance R_L to reduce the errors of the generated power P_L. Similarly, to keep the resistive load current I_L and the resistive image current I_D1 nearly equal, the design [15] assumes that the resistances within the unity gain differential amplifier have to be much larger (220 kΩ) than the largest load resistance R_L to reduce the errors of the generated power P_L. Such large resistances should be avoided in an integrated technology due to large chip area. For this reason, in the case of possible realization of the CCPS [14, 15] in an integrated technology, these resistances should be reduced, and the voltage at the common terminal made by the inverting input of the operational amplifier, resistive load R_L and the drain of M₁ should be buffered towards one of the inputs of the resistive voltage divider [14] and differential amplifier [15] via a voltage follower. This would lead to a more complex design relative to the proposed one shown in Fig. 1. So, the CCPSs [14, 15] are not very suitable for the integrated technology implementation. Because the proposed CCPS has no systematic error as described above, it can be expected that the generated power dynamic range P_Lmax/P_Lmin and the load resistance dynamic range R_Lmax/R_Lmin of the proposed CCPS will be larger than those in [14, 15], assuming the same relative error and the same output voltage swing of the operational amplifiers used in these designs.

The complete circuit schematic of the proposed resistive mirror based CCPS is shown in Fig. 1 (right). The resistive load R_L is put outside the chip. Both of OA₁ and OA₂ are designed as telescopic cascoded ones [20,21,22,23,24,25,26,27]. The differential input stages are designed in the form of common source—common gate amplifiers with M₃ and M₅, as well as M₄ and M₆ (M₁₅ and M₁₇, as well as M₁₆ and M₁₈), with the biasing voltages V_B2 and V_B5. The active loads are designed as wide swing current mirrors made by M₇–M₁₀ (M₁₉–M₂₂) with the biasing voltage V_B4. The DC biasing currents are generated by M₁₁ (M₂₃), with the biasing voltage V_B1. In order to provide regular operation of these operational amplifiers with small input voltages (< 100 mV), simple source followers are placed at the inputs. All of these source followers act as DC voltage level shifters. The source followers at the inputs of OA₁ are designed by the matched p-channel M₁₂ and M₁₃, and the resistors with the resistances R₃ = R₄, with the biasing voltage V_B3. The source followers at the inputs of OA₂ are designed by the matched p-channel M₂₄ and M₂₅, and the resistors with the resistances R₅ = R₆, with the biasing voltages V_B6 and V_B7. The DC voltage V_B (4) is generated as the difference of the input voltages of OA₂ by making appropriate difference between the DC biasing voltages V_B6 and V_B7. It is sufficient to change either V_B6 or V_B7 DC biasing voltage. In both HV CCPS and LV CCPS the biasing voltage V_B6 has been kept constant and equal to V_B3, while the biasing voltage V_B7 has been adjusted. Assuming a simple quadratic model of saturated MOSFET [18,19,20], the DC voltage V_B is given by

$$ V_{B} \approx \sqrt {{2 \mathord{\left/ {\vphantom {2 {\left( {\beta_{24} R_{5} } \right)}}} \right. \kern-0pt} {\left( {\beta_{24} R_{5} } \right)}}} \left( {\sqrt {V_{t24} + V_{B6} } - \sqrt {V_{t25} + V_{B7} } } \right) + V_{OFFDA2} $$

(7)

where V_t24 = V_t25 are the threshold voltages of M₂₄ and M₂₅, respectively, β₂₄ = β₂₅ are the transconductance parameters of M₂₄ and M₂₅, respectively, and V_OFFDA2 is the offset voltage caused by the imperfections of the differential amplifier made by M₁₅ and M₁₆. By appropriate adjustment of the biasing voltage V_B7, the required value of the DC voltage V_B can be achieved. The following approximations have been applied: V_DS2 ≪ V_t24 + V_B6, V_DS2 ≪ V_t25 + V_B7, 2β₂₄R₅(V_t24 + V_B6) ≫ 1, and 2β₂₅R₆(V_t25 + V_B7) ≫ 1. The output stage of OA₁ is presented by the source follower with M₁₄, biased by the resistive voltage divider R₁–R₂, the resistive load R_L, and the resistive image M₁. Because the output of OA₂ is only connected to the gates of M₁ and M₂, there is no output stage of OA₂. The capacitor C_C1 is used for the frequency compensation of OA₁ for both the HV CCPS and the LV CCPS. Due to the large dimensions of M₁ and M₂ used in the HV CCPS, their built-in gate-to-source and gate-to-drain capacitances, C_gs1 and C_gs2, as well as C_gd1 and C_gd2, respectively, are large enough for the frequency compensation of OA₂. Due to relative small dimensions of M₁ and M₂ used in the LV CCPS, the mentioned parasitic capacitances are not large enough, and the compensation capacitor C_C2 is applied. The reference current source I_REF is designed in the form of the voltage-controlled current source using the first generation current conveyor (CCI) [28] with M₂₆–M₃₅, the resistor R₇, and the control voltage source V_C. The reference current I_REF is given by

$$ I_{REF} = {{mV_{C} } \mathord{\left/ {\vphantom {{mV_{C} } {R_{7} }}} \right. \kern-0pt} {R_{7} }} $$

(8)

where m is the current gain of the two-output current mirror made by M₃₀–M₃₅. By using the relation (8), the generated power P_L (6) can be expressed as follows

$$ P_{L} = \frac{m}{{k_{R12} }}\frac{{V_{REF} V_{C} }}{{R_{7} }} = m\left( {1 + \frac{{R_{1} }}{{R_{2} }}} \right)\frac{{V_{REF} V_{C} }}{{R_{7} }} . $$

(9)

3 Temperature influence

The generated power P_L (6), (9) of the proposed CCPS is influenced by the temperature variations due to the temperature dependences of the reference voltage V_REF, the reference current I_REF, as well as the offset voltages V_OFFOA1, V_OFFOA2, and V_OFFCCI of OA₁, OA₂, and the voltage follower part of the CCI, respectively.

3.1 Temperature dependence of the reference voltage and the reference current

The reference voltage V_REF and the control voltage V_C are designed using off-chip potentiometers powered by the supply voltage V_DD. So, the reference and the control voltage are expressed as follows: V_REF = k_P1V_DD and V_C = k_P2V_DD, where k_P1 and k_P2 are the magnitudes of the attenuation of the potentiometers used. The generated power P_L (9) can be written in the following form:

$$ P_{L} = m\left( {1 + \frac{{R_{1} }}{{R_{2} }}} \right)k_{P1} k_{P2} \frac{{V_{DD}^{2} }}{{R_{7} }} $$

(10)

The normalized temperature coefficient (∂P_L/∂T)/P_L of the generated power P_L (10) is calculated as

$$ \frac{1}{{P_{L} }}\frac{{\partial P_{L} }}{\partial T} = 2\frac{1}{{V_{DD} }}\frac{{\partial V_{DD} }}{\partial T} - \frac{1}{{R_{7} }}\frac{{\partial R_{7} }}{\partial T} $$

(11)

So, the normalized temperature coefficient (∂V_DD/∂T)/V_DD of the supply voltage V_DD must be two times smaller than the normalized temperature coefficient (∂R₇/∂T)/R₇ of the resistance R₇ in order to achieve the normalized temperature coefficient of the generated power P_L equal to zero. This is a difficult task because of unpredictable values of the normalized temperature coefficients of the supply voltage V_DD and the resistance R₇. In order to achieve (∂P_L/∂T)/P_L ≈ 0, the supply voltage source V_DD should be realized as a voltage reference circuit with a small enough value (∂V_DD/∂T)/V_DD, and to achieve the value (∂R₇/∂T)/R₇ nearly equal to zero by implementing a series or parallel composite resistor [29,30,31]. The resistor R₇ is designed by using two resistors R_7A and R_7B coupled together in series, R₇ = R_7A + R_7B. The normalized temperature coefficients of their resistances (∂R_7A/∂T)/R_7A and (∂R_7B/∂T)/R_7B must have different polarity. Hence, the normalized temperature coefficient (∂R₇/∂T)/R₇ of the total resistance R₇ is given by [30, 31]

$$ \frac{1}{{R_{7} }}\frac{{\partial R_{7} }}{\partial T} = \frac{{R_{7A} }}{{R_{7} }}\left( {\frac{1}{{R_{7A} }}\frac{{\partial R_{7A} }}{\partial T}} \right) + \frac{{R_{7B} }}{{R_{7} }}\left( {\frac{1}{{R_{7B} }}\frac{{\partial R_{7B} }}{\partial T}} \right) $$

(12)

In order to achieve (∂R₇/∂T)/R₇ = 0, the following condition must be fulfilled:

$$ \frac{{R_{7A} }}{{R_{7B} }} = - \frac{{{{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7B} }}} \right. \kern-0pt} {R_{7B} }}}}{{{{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7A} }}} \right. \kern-0pt} {R_{7A} }}}} $$

(13)

The relation (13), together with R₇ = R_7A + R_7B, leads to the following values of the resistances R_7A and R_7B

$$ R_{7A} = \frac{{{{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7B} }}} \right. \kern-0pt} {R_{7B} }}}}{{{{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7B} }}} \right. \kern-0pt} {R_{7B} }} - {{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7A} }}} \right. \kern-0pt} {R_{7A} }}}}R_{7} $$

(14)

$$ R_{7B} = \frac{{{{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7A} }}} \right. \kern-0pt} {R_{7A} }}}}{{{{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7A} } \mathord{\left/ {\vphantom {{\partial R_{7A} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7A} }}} \right. \kern-0pt} {R_{7A} }} - {{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} \mathord{\left/ {\vphantom {{\left( {{{\partial R_{7B} } \mathord{\left/ {\vphantom {{\partial R_{7B} } {\partial T}}} \right. \kern-0pt} {\partial T}}} \right)} {R_{7B} }}} \right. \kern-0pt} {R_{7B} }}}}R_{7} $$

(15)

In order to reduce the sensitivity of the normalized temperature coefficient to process variations, the parallel/series or series/parallel composite resistor can be implemented [30, 31]. Using these topologies, a normalized temperature coefficient of the total resistance is almost insensitive to process variations, unlike in the simple series and simple parallel composite resistors.

3.2 Temperature dependence of the offset voltages

The offset voltage V_OFFOA1 of OA₁ can be calculated as V_OFFOA1 = V_OFFSF1 + V_OFFDA1, where V_OFFSF1 is the offset voltage caused by the imperfections of the source followers made by M₁₂ and M₁₃ and V_OFFDA1 is the offset voltage caused by the imperfections of the differential amplifier made by M₃ and M₄ [20]. The offset voltage V_OFFSF1 caused by the imperfections of the source followers made by M₁₂ and M₁₃ can be calculated as follows

$$ V_{OFFSF1} \approx \Delta V_{t1213} + \sqrt {\frac{{V_{B3} + V_{t1213} }}{{2\beta_{1213} R_{34} }}} \left( {\frac{{\Delta \beta_{1213} }}{{\beta_{1213} }} + \frac{{\Delta R_{34} }}{{R_{34} }} - \frac{{\Delta V_{t1213} }}{{V_{B3} + V_{t1213} }}} \right) $$

(16)

where ΔV_t1213 = V_t12− V_t13, V_t1213 = (V_t12 + V_t13)/2, Δβ₁₂₁₃ = β₁₂− β₁₃, β₁₂₁₃ = (β₁₂ + β₁₃)/2, ΔR₃₄ = R₃− R₄, and R₃₄ = (R₃ + R₄)/2. Here, V_t12 and V_t13 are the threshold voltages of M₁₂ and M₁₃, respectively, β₁₂ and β₁₃ are the transconductance parameters of M₁₂ and M₁₃, respectively. The offset voltage V_OFFDA1 caused by the imperfections of the differential amplifier made by M₃ and M₄ is given by

$$ V_{OFFDA1} \approx \Delta V_{t34} + \sqrt {\frac{{\beta_{78} }}{{\beta_{34} }}} \Delta V_{t78} + \sqrt {\frac{{I_{D34} }}{{2\beta_{34} }}} \left( {\frac{{\Delta \beta_{78} }}{{\beta_{78} }} - \frac{{\Delta \beta_{34} }}{{\beta_{34} }}} \right) $$

(17)

where ΔV_t34 = V_t3 − V_t4, ΔV_t78 = V_t7 − V_t8, Δβ₃₄ = β₃ − β₄, β₃₄ = (β₃ + β₄)/2, Δβ₇₈ = β₇ − β₈, β₇₈ = (β₇ + β₈)/2, I_D34 = (I_D3 + I_D4)/2. Here, V_t3, V_t4, V_t7, and V_t8 are the threshold voltages of M₃, M₄, M₇, and M₈, respectively, β₃, β₄, β₇, and β₈ are the transconductance parameters of M₃, M₄, M₇, and M₈, respectively, and I_D3 and I_D4 are the drain currents of M₃ and M₄, respectively. The temperature coefficient ∂V_OFFSOA1/∂T = ∂V_OFFSF1/∂T + ∂V_OFFSDA1/∂T is the following

$$ \begin{aligned} \frac{{\partial V_{OFFOA1} }}{\partial T} & \approx \frac{1}{2}\left( {V_{OFFSF1} - \Delta V_{t1213} } \right)\left[ {\frac{1}{{V_{B3} + V_{t1213} }}\frac{{\partial \left( {V_{B3} + V_{t1213} } \right)}}{\partial T} - \frac{1}{{\beta_{1213} }}\frac{{\partial \beta_{1213} }}{\partial T} - \frac{1}{{R_{34} }}\frac{{\partial R_{34} }}{\partial T}} \right] \\ & \quad + \frac{1}{2}\Delta V_{t78} \sqrt {\frac{{\beta_{78} }}{{\beta_{34} }}} \left( {\frac{1}{{\beta_{78} }}\frac{{\partial \beta_{78} }}{\partial T} - \frac{1}{{\beta_{34} }}\frac{{\partial \beta_{34} }}{\partial T}} \right) \\ & \quad + \frac{1}{2}\left( {V_{OFFDA1} - \Delta V_{t34} - \sqrt {\frac{{\beta_{78} }}{{\beta_{34} }}} \Delta V_{t78} } \right)\left( {\frac{1}{{I_{D34} }}\frac{{\partial I_{D34} }}{\partial T} - \frac{1}{{\beta_{34} }}\frac{{\partial \beta_{34} }}{\partial T}} \right) \\ \end{aligned} $$

(18)

By increasing β₁₂₁₃ = (β₁₂ + β₁₃)/2 and R₃₄ = (R₃ + R₄)/2, as well as by decreasing V_B3, the relation (16) can be approximated as V_OFFSF1 ≈ ΔV_t1213. By increasing β₃₄ = (β₃ + β₄)/2 and decreasing I_D34 = (I_D3 + I_D4)/2, the relation (17) can be approximated as V_OFFDA1 ≈ ΔV_t34 + (β₇₈/β₃₄)^1/2ΔV_t78. In this way, the temperature coefficient ∂V_OFFSOA1/∂T (18) becomes dominantly determined by the difference of the temperature coefficients of the electron mobility in M₃, M₄ and the hole mobility in M₇, M₈ (the middle term in the relation 18). So, with the same order of the concentrations of the electrons in the channels of M₃ and M₄, and the holes in the channels of M₇ and M₈, the temperature coefficient ∂V_OFFSOA1/∂T (18) can be made sufficiently small [18, 32].

The offset voltage V_OFFOA2 of OA₂ can be calculated as V_OFFOA2 = V_OFFSF2 + V_OFFDA2, where V_OFFSF2 is the offset voltage caused by the imperfections of the source followers made by M₂₄ and M₂₅, and V_OFFDA2 is the offset voltage caused by the imperfections of the differential amplifier made by M₁₅ and M₁₆ [20]. The offset voltage V_OFFSF2 caused by the imperfections of the source followers made by M₂₄ and M₂₅ can be calculated as follows

$$ V_{OFFSF2} \approx \Delta V_{t2425} + \sqrt {\frac{{V_{B67} + V_{t2425} }}{{2\beta_{2425} R_{56} }}} \left( {\frac{{\Delta \beta_{2425} }}{{\beta_{2425} }} + \frac{{\Delta R_{56} }}{{R_{56} }} - \frac{{\Delta V_{B67} + \Delta V_{t2425} }}{{V_{B67} + V_{t2425} }}} \right) $$

(19)

where ΔV_t2425 = V_t24 − V_t25, V_t2425 = (V_t24 + V_t25)/2, ΔV_B67 = V_B6 − V_B7, V_B67 = (V_B6 + V_B7)/2, Δβ₂₄₂₅ = β₂₄ − β₂₅, β₂₄₂₅ = (β₂₄ + β₂₅)/2, ΔR₅₆ = R₅ − R₆, and R₅₆ = (R₅ + R₆)/2. Here, V_t24 and V_t25 are the threshold voltages of M₂₄ and M₂₅, respectively, β₂₄ and β₂₅ are the transconductance parameters of M₂₄ and M₂₅, respectively. The offset voltage V_OFFDA2 caused by the imperfections of the differential amplifier made by M₁₅ and M₁₆ is given by

$$ V_{OFFDA2} \approx \Delta V_{t1516} + \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \Delta V_{t1920} + \sqrt {\frac{{I_{D1516} }}{{2\beta_{1516} }}} \left( {\frac{{\Delta \beta_{1920} }}{{\beta_{1920} }} - \frac{{\Delta \beta_{1516} }}{{\beta_{1516} }}} \right) $$

(20)

Here, ΔV_t1516 = V_t15 − V_t16, ΔV_t1920 = V_t19 − V_t20, β₁₅₁₆ = (β₁₅ + β₁₆)/2, β₁₉₂₀ = (β₁₉ + β₂₀)/2, I_D1516 = (I_D15 + I_D16)/2. Here, V_t15, V_t16, V_t19 and V_t20 are the threshold voltages of M₁₅, M₁₆, M₁₉ and M₂₀, respectively, β₁₅, β₁₆, β₁₉ and β₂₀ are the transconductance parameters of M₁₅, M₁₆, M₁₉, and M₂₀, respectively, and I_D15 and I_D16 are the drain currents of M₁₅ and M₁₆, respectively. The temperature coefficient ∂V_OFFSOA2/∂T = ∂V_OFFSF2/∂T + ∂V_OFFSDA2/∂T is the following

$$ \begin{aligned} \frac{{\partial V_{OFFOA2} }}{\partial T} & \approx \frac{1}{2}\left( {V_{OFFSF2} - \Delta V_{t2425} } \right)\left[ {\frac{1}{{V_{B67} + V_{t2425} }}\frac{{\partial \left( {V_{B67} + V_{t2425} } \right)}}{\partial T} - \frac{1}{{\beta_{2425} }}\frac{{\partial \beta_{2425} }}{\partial T} - \frac{1}{{R_{56} }}\frac{{\partial R_{56} }}{\partial T}} \right] \\ & \quad + \frac{1}{2}\Delta V_{t1920} \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \left( {\frac{1}{{\beta_{1920} }}\frac{{\partial \beta_{1920} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ & \quad + \frac{1}{2}\left( {V_{OFFDA2} - \Delta V_{t1516} - \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \Delta V_{t1920} } \right)\left( {\frac{1}{{I_{D1516} }}\frac{{\partial I_{D1516} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ \end{aligned} $$

(21)

By increasing β₂₄₂₅ = (β₂₄ + β₂₅)/2 and R₅₆ = (R₅ + R₆)/2, as well as by decreasing V_B67 = (V_B6 + V_B7)/2, the relation (19) can be approximated as V_OFFSF2 ≈ ΔV_t2425. By increasing β₁₅₁₆ = (β₁₅ + β₁₆)/2 and decreasing I_D1516 = (I_D15 + I_D16)/2, the relation (20) can be approximated as V_OFFDA2 ≈ ΔV_t1516 + (β₁₉₂₀/β₁₅₁₆)^1/2ΔV_t1920. In this way, the temperature coefficient ∂V_OFFSOA2/∂T (21) becomes dominantly determined by the difference of the temperature coefficients of the electron mobility in M₁₅, M₁₆, and the hole mobility in M₁₉, M₂₀ (the middle term in the relation 21). So, with the same order of the concentrations of the electrons in the channels of M₁₅ and M₁₆, and the holes in the channels of M₁₉ and M₂₀, the temperature coefficient ∂V_OFFSOA2/∂T (21) can be made sufficiently small [18, 32].

The difference in the temperature coefficients (18) and (21) is caused by the different biasing voltages V_B3 = V_B6 and V_B7. While the temperature coefficient ∂V_OFFSOA1/∂T (18) is influenced by the temperature coefficient of the biasing voltage V_B3 = V_B6, the temperature coefficient ∂V_OFFSOA2/∂T (21) is influenced by the temperature coefficient of the common-mode value of the biasing voltages V_B3 = V_B6 and V_B7. If the DC biasing voltages V_B3 = V_B6 and V_B7 originate from the same voltage source (e.g. supply voltage source V_DD) using resistive voltage dividers, there is no difference between the temperature coefficients of the biasing voltages V_B3 = V_B6 and V_B67 = (V_B6 + V_B7)/2.

The offset voltage V_OFFCCI of the voltage follower part of the CCI can be calculated as follows

$$ V_{OFFCCI} \approx \Delta V_{t2627} + \sqrt {\frac{{\beta_{3031} }}{{\beta_{2627} }}} \Delta V_{t3031} + \sqrt {\frac{{I_{D2627} }}{{2\beta_{2627} }}} \left( {\frac{{\Delta \beta_{3031} }}{{\beta_{3031} }} - \frac{{\Delta \beta_{2627} }}{{\beta_{2627} }}} \right) $$

(22)

where ΔV_t2627 = V_t26 − V_t27, ΔV_t3031 = V_t30 − V_t31, Δβ₂₆₂₇ = β₂₆ − β₂₇, β₂₆₂₇ = (β₂₆ + β₂₇)/2, Δβ₃₀₃₁ = β₃₀ − β₃₁, β₃₀₃₁ = (β₃₀ + β₃₁)/2, I_D2627 = (I_D26 + I_D27)/2. Here, V_t26, V_t27, V_t30 and V_t31 are the threshold voltages of M₂₆, M₂₇, M₃₀, and M₃₁, respectively, β₂₆, β₂₇, β₃₀, and β₃₁ are the transconductance parameters of M₂₆, M₂₇, M₃₀, M₃₁, respectively, and I_D26 and I_D27 are the drain currents of M₂₆ and M₂₇, respectively. The temperature coefficient ∂V_OFFCCI/∂T is given by

$$ \begin{aligned} \frac{{\partial V_{OFFCCI} }}{\partial T} & \approx \frac{1}{2}\Delta V_{t3031} \sqrt {\frac{{\beta_{3031} }}{{\beta_{2627} }}} \left( {\frac{1}{{\beta_{3031} }}\frac{{\partial \beta_{3031} }}{\partial T} - \frac{1}{{\beta_{2627} }}\frac{{\partial \beta_{2627} }}{\partial T}} \right) \\ & \quad + \frac{1}{2}\left( {V_{OFFCCI} - \Delta V_{t2627} - \sqrt {\frac{{\beta_{3031} }}{{\beta_{2627} }}} \Delta V_{t3031} } \right)\left( {\frac{1}{{I_{D2627} }}\frac{{\partial I_{2627} }}{\partial T} - \frac{1}{{\beta_{2627} }}\frac{{\partial \beta_{2627} }}{\partial T}} \right) \\ \end{aligned} $$

(23)

By increasing β₂₆₂₇ = (β₂₆ + β₂₇)/2 and decreasing I_D2627 = (I_D26 + I_D27)/2, the relation (22) can be approximated as V_OFFCCI ≈ ΔV_t2627 + (β₃₀₃₁/β₂₆₂₇)^1/2ΔV_t3031. In this way, the temperature coefficient ∂V_OFFSCCI/∂T (23) becomes dominantly determined by the difference of the temperature coefficients of the electron mobility in M₂₆, M₂₇, and the hole mobility in M₃₀, M₃₁ (the first term in the relation 23). So, with the same order of the concentrations of the electrons in the channels of M₂₆ and M₂₇, and the holes in the channels of M₃₀ and M₃₁, the temperature coefficient ∂V_OFFSCCI/∂T (23) can be made sufficiently small [18, 32].

4 Stability

The small-signal equivalent circuit for the calculation of the loop-gain Aβ(s) of the proposed CCPS is shown in Fig. 2. The frequency transfer characteristics of OA₁ and OA₂, A_i(s) = A_0i/(1 + s/ω_bi), i ∈ {1, 2}, are modelled by the dominant poles ω_bi and the DC gains A_0i [19, 20]. A small-signal analysis of the CCPS using the equivalent circuit shown in Fig. 2(a) leads to the following expression for the loop-gain Aβ(s)

$$ A\beta \left( s \right) = - \frac{{v_{gs2} }}{{v_{t} }} \approx \frac{1}{{\left( {1 + {s \mathord{\left/ {\vphantom {s {\omega_{p1} }}} \right. \kern-0pt} {\omega_{p1} }}} \right)\left( {1 + {s \mathord{\left/ {\vphantom {s {\omega_{p2} }}} \right. \kern-0pt} {\omega_{p2} }}} \right)}} $$

(24)

where v_gs2 is the gate-to-source voltage of M₂, and v_t is the test voltage, while the poles ω_p1 and ω_p2 are given by

Fig. 2: a

Small-signal equivalent circuit for the calculation of the loop-gain Aβ(s) of the proposed CCPS and b the absolute value |Aβ(s = jω)|_dB and the phase φ(ω) of the loop-gain Aβ(s), with ω_p1 < ω_p2

$$ \omega_{p1} = \frac{{r_{ds1} }}{{r_{ds1} + R_{L} }}A_{01} \omega_{b1} = \frac{{V_{REF} }}{{V_{REF} + V_{L} }}A_{01} \omega_{b1} $$

(25)

$$ \omega_{p2} = g_{m2} r_{ds2} A_{02} \omega_{b2} = k_{R12} \beta_{1} V_{REF} R_{L} A_{02} \omega_{b2} $$

(26)

Unlike in [15], where the loop-gain Aβ(s) has three poles and one zero, the loop-gain Aβ(s) of the proposed CCPS has only two poles. These two poles are real and different, and placed in the left half-plane. The parameters of interest in the relations (25) and (26) are the following: the output resistances r_ds1 = R_DS1 (2) and r_ds2 = R_DS2 (5) of the non-saturated M₁ and M₂, respectively, and the transconductance g_m2 = β₂V_DS2 = k_R12β₂V_L of M₂. Because of the resistive load voltage V_L, the pole ω_p1 (25) is dependent on both the load resistance R_L and the generated power P_L. On the other hand, assuming a constant value of the reference voltage, V_REF = const., the pole ω_p2 (26) is dependent on the load resistance R_L, and not on the generated power P_L. It means that the pole ω_p2 (26) is the same for each generated power P_L, for a certain value of the load resistance R_L, with V_REF = const. For the load resistance range and the generated power range of interest, as well as for the values of the transconductance parameters used β₁ = β₂, the parameter determining the pole ω_p2 (26) fulfills the following inequality: g_m2r_ds2 = k_R12β₁V_REFR_L < 1. Depending on the load resistance R_L and the generated power P_L, assuming that the gain-bandwidth products A₀₁ω_b1 and A₀₂ω_b2 of OA₁ and OA₂, respectively, are nearly equal, A₀₁ω_b1 ≈ A₀₂ω_b2, both of the following inequalities are possible: ω_p1 < ω_p2, and ω_p1 > ω_p2. The absolute value |Aβ(s = jω)|_dB = 20 log|Aβ(s = jω)| and the phase φ(ω) of the loop-gain Aβ (s) (24), with ω_p1 < ω_p2, are shown in Fig. 2(b). Because |Aβ (s = jω)| = 1 (|Aβ (s = jω)|_dB = 0) for ω < min{ω_p1, ω_p2}, and there is no zero in the loop-gain Aβ(s) (24), the proposed CCPS is unconditionally stable. So, the stability of the proposed CCPS is not dependent either on the load resistance R_L or the generated power P_L. This achievement presents a significant improvement compared to that in [14], where the stability depends on both the load resistance R_L and the generated power P_L.

5 Error analysis

The main sources of the errors in the proposed CCPS are the offset voltages of the operational amplifiers used and different values of the drain-to-source voltages of M₁ and M₂. Because the analysis of the error caused by the different values of the drain-to-source voltages of M₁ and M₂ performed in [14, 15] is also valid for the proposed CCPS, only the error analysis caused by the offset voltages of the operational amplifiers used will be considered.

Taking into account the offset voltage V_OFF1 and V_OFF2 of OA₁ and OA₂, respectively, the drain-to-source voltages V_DS1 and V_DS2 of M₁ and M₂ can be expressed as follows

$$ V_{DS1} = V_{REF} + V_{OFF1} $$

(27)

$$ V_{DS2} = k_{R12} \left( {V_{REF} + V_{OFF1} + V_{L} } \right) + V_{OFF2} - V_{B} $$

(28)

Neglecting the influence of the different values of the drain-to-source voltages of M₁ and M₂, and assuming the equality of the channel resistances R_DS1 and R_DS2 of M₁ and M₂, respectively, the following expression for the generated power P_L is obtained

$$ P_{L} = V_{L} I_{L} = \frac{1}{{k_{R12} }}\left( {V_{REF} + V_{OFF1} } \right)I_{REF} - \left[ {\frac{1}{{k_{R12} }}\left( {V_{OFF2} - V_{B} } \right) + V_{REF} + V_{OFF1} } \right]I_{L} $$

(29)

The relative error E_R of the generated power P_L caused by the offset voltages V_OFF1 and V_OFF2 of OA₁ and OA₂, respectively, can be expressed as follows

$$ E_{R} \left[ \% \right] = \frac{1}{{V_{REF} }}\left\{ { - V_{OFF1} + \left[ {V_{OFF2} + k_{R12} \left( {V_{REF} + V_{OFF1} } \right) - V_{B} } \right]\frac{{I_{L} }}{{I_{REF} }}} \right\} \cdot 100 $$

(30)

Similar to [15], the relative error E_R (30) caused by the offset voltages of the operational amplifiers used is inversely proportional to the reference voltage V_REF, and directly proportional to the ratio I_L/I_REF of the resistive load current I_L and the reference current I_REF. In order to achieve the relative error E_R = 0, the following value of the DC voltage V_B should be applied:

$$ V_{B} = k_{R12} V_{REF} + V_{OFF2} + \left( {k_{R12} - \frac{{I_{REF} }}{{I_{L} }}} \right)V_{OFF1} $$

(31)

A short comparison of three relations describing the DC voltage V_B (4), (7), and (31) can be performed as follows. The relation (4) has been derived assuming the ideal operation of OA₁ and OA₂. On the other hand, the relation (7) has been derived taking into account the offset voltage caused by the imperfections of the differential amplifier made by M₁₅ and M₁₆. The relation (31) is derived starting from the goal of achieving the relative error E_R (30) equal to zero, E_R = 0. By fulfilment of the relation (31), the influence of the offset voltages V_OFF1 and V_OFF2 on the operation of the proposed CCPS is cancelled out. The value of the DC voltage V_B (31) can be achieved by a simple calibration procedure explained as follows. For an arbitrary load resistance R_L from the range of the interest (R_Lmin < R_L < R_Lmax), and for the certain values of the reference voltage V_REF and the reference current I_REF, with the known value of the coefficient k_R12, the biasing voltage V_B7 should be adjusted until the generated power P_L achieves the value determined by the relation (6). Now, the value of the DC voltage V_B achieves the value given by (31). It can be seen from the relation (31) that the value k_R12V_REF expressed by the relation (4) is affected by the offset voltage V_OFF1 and V_OFF2 of the operational amplifiers used. However, by applying the calibration procedure described above, the influence of the offset voltages V_OFF1 and V_OFF2 is cancelled out. The calibration is also necessary in the CCPS [15], and it is performed by adjustments of the resistance ratio within the source followers at the inputs of the operational amplifiers used.

Because the calibration procedure cannot be perfectly performed, the relative error E_R (30) will still exist, but to a much lesser extent. It can be shown that by decreasing the generated power P_L the ratio of the resistive load current and the reference current I_L/I_REF is increased. Consequently, the relative error E_R (30) will also be increased. So, it can be expected that the largest errors will be occurred for the smallest generated powers P_L.

6 Measured and simulated results

The proposed HV CCPS and LV CCPS have been designed in 0.35 μm CMOS technology. The chip microphotographs are shown in Fig. 3. The active area of the HV CCPS chip is 990 μm × 550 μm. The active area of the LV CCPS chip is 610 μm × 330 μm. The chips have been glued on a printed circuit board and wire-bonded to it. The value of the DC voltage V_B (31) has been provided by the adjustment of the DC biasing voltage V_B7, while the biasing voltage V_B6 has been kept constant, within the calibration procedure for both HV CCPS and LV CCPS. There is only one DC biasing voltage source for providing the voltages V_B2 and V_B5, because the condition V_B2 = V_B5 always holds, for both HV CCPS and LV CCPS. Also, there is only one DC biasing voltage source for providing the voltages V_B3 and V_B6, because the condition V_B3 = V_B6 always holds, for both HV CCPS and LV CCPS. In addition, the DC biasing voltage V_B3 could be replaced by the supply voltage source V_DD, at the price of increased power consumption. So, the proposed design requires the following five DC biasing voltage sources: V_B1, V_B2 = V_B5, V_B3 = V_B6, V_B4, and V_B7. And only one of them (V_B7) has to be accurately adjusted by the calibration procedure. A possible design for on-chip generation of the DC biasing voltages V_B1, V_B2 = V_B5, and V_B4 can be found in [20, 21, 33, 34]. A possible design for on-chip generation of the DC biasing voltages V_B3 = V_B6 and the resistors R₃ = R₄ = R₅ can be found in [35]. The parasitic elements at both of the terminals of the resistive loads R_L put outside the chips are the following: bond-wire inductors (≈ 3 nH per bond-wire), printed circuit board capacitors (≈ 3 pF per terminal), oscilloscope probe capacitors (≈ 12 pF per probe), and the capacitors (≈ 8 pF) of the bilateral CMOS switch within the resistive load in the pulse mode operation. Measured transient responses have been recorded by a LeCroy WR204Xi oscilloscope (2-GHz bandwidth, 10 GS/s). The temperature measurements have been performed by using a precision temperature forcing system Thermonics T-2650BV (accuracy: ± 1 °C, stability: ± 0.3 °C). Measured and simulated results for HV CCPS and LV CCPS will be presented separately. Comparison between the proposed CCPS and the state-of-the-art is given in Table 1.

Fig. 3

Chip microphotographs: a HV CCPS and b LV CCPS

Table 1 Comparison between the proposed CCPS and state-of-the-art

6.1 Measured and simulated results for HV CCPS

The following supply, biasing, reference, and control voltages have been used for the HV CCPS: V_DD = 10 V, V_B1 = 1.55 V, V_B2 = V_B5 = 2.2 V, V_B3 = V_B6 = 3.2 V, V_B4 = 7.7 V, V_B7 = 3.15 V, V_REF ∈ {50 mV, 100 mV}, and 2.5 mV < V_C < 706 mV. The estimated equivalent transconductance parameters β₁ and β₂ of M₁ and M₂ are β₁ = β₂ ≈ 90 mA/V². The variable resistive load R_L with the resistance range 0.28 kΩ < R_L < 1.68 kΩ is put outside the chip. The resistances of the resistors used inside the chip are the following: R₁ = R₃ = R₄ = R₅ = R₆ = 20 kΩ, R₂ = 0.3 kΩ and R₇ = 0.8 kΩ. The value of the coefficient k_R12 is calculated as k_R12 = 0.0148. For the load resistance range mentioned above, for the generated power range 40 μW < P_L < 30 mW, assuming that V_REF = 100 mV, the parameters determining the poles ω_p1 (25) and ω_p2 (26) range as follows: 0.014 < r_ds1/(r_ds1 + R_L) < 0.486, and 0.037 < g_m2r_ds2 < 0.222. The resistor R₇ is designed by using two resistors R_7A and R_7B coupled together in series, with the resistance R₇ = R_7A + R_7B. The resistor R_7A is made by using an N+HRES polysilicon resistor with a typical value of the linear temperature coefficient (∂R_7A/∂T)/R_7A = − 2.9∙10⁻³/K, while the resistor R_7B is made by using an N-well resistor with a typical value of the linear temperature coefficient (∂R_7B/∂T)/R_7B = + 3.9∙10⁻³/K. So, the resistances of the composite resistor R₇ are the following: R_7A ≈ 460 Ω (14) and R_7B ≈ 340 Ω (15). The capacitor C_C1 used for the frequency compensation of OA₁ has the capacitance C_C1 = 2.5 pF. The channel lengths of the MOSFETs used are fixed (1.1 μm for n-channel MOSFETs, 1.7 μm for p-channel MOSFETs, and 0.8 μm for the isolated n-channel MOSFET M₁₄). Consequently, the channel widths of M₁, M₂, M₁₄, M₃₂, and M₃₅ have to be quite large in order to achieve large enough corresponding transconductance parameters. The typical absolute values of the threshold voltages V_tn and |V_tp| of the n-channel and p-channel MOSFETs are the following: V_tn ≈ |V_tp| ≈ 1.35 V. The isolated MOSFETs M₁₄ have a drain-to-source breakdown voltage of 20 V. The rest of n-channel MOSFETs and all p-channel MOSFETs have drain-to-source (source-to-drain) breakdown voltages of 50 V.

The post-layout simulations of the open-loop gain and phase frequency transfer characteristics of OA₁ within the HV CCPS are shown in Fig. 4. The simulations have been performed by using CADENCE software tools. The resistive load R_L at the output of OA₁ has the resistance equal to the middle of the load resistance range: R_L = 0.98 kΩ. In addition to the resistive load R_L, there are also bond-wire inductors with inductances L_BW1 = L_BW2 = 3 nH, the capacitors of the printed circuit board and oscilloscope probes with capacitances C_PCB1 = C_PCB2 = 10 pF, and the channel resistance R_DS1 = 31 Ω (corresponding to R_L = 0.98 kΩ and P_L = 10 mW) as well as the resistive voltage divider R₁-R₂, with R₁ = 20 kΩ and R₂ = 0.3 kΩ. The simulations have shown a DC gain of 97.1 dB, a unity-gain frequency of 6.1 MHz, and a phase margin of 74.7⁰. Similar simulated results have been achieved for OA₂ within the HV CCPS, as well as for both OA₁ and OA₂ within the LV CCPS.

Fig. 4

Simulations of the open-loop gain and phase frequency transfer characteristics of OA₁, with the circuit schematic of the load impedance

Measured generated power P_L versus load resistance R_L of the proposed HV CCPS, for different values of the reference current I_REF, and for the fixed values of the reference voltage V_REF, are shown in Fig. 5(a)–(c). While the load resistance R_L has been changed from 0.28 to 1.68 kΩ in steps of 140 Ω, the generated power P_L has been kept constant. The relative errors E_R of the generated power P_L versus load resistance R_L shown in Fig. 6 are calculated corresponding to the generated power P_L measured for the middle of the load resistance range, i.e., for R_L = 0.98 kΩ. These relative errors for the HV CCPS are smaller than 1% for the generated power P_L in the range 80 μW ≤ P_L ≤ 30 mW. For the generated power P_L < 80 μW the relative error E_R increases. The largest relative error E_R = − 1.8% occurs for the smallest generated power of P_L = 40 μW. In this way, the predictions of the analysis performed in the Sect. 5 Error analysis have been confirmed. So, for the HV CCPS the generated power dynamic range is P_Lmax/P_Lmin = 750 (57.5 dB) for the load resistance dynamic range R_Lmax/R_Lmin = 6 (15.6 dB).

Fig. 5

Measured generated power P_L versus load resistance R_L of the proposed HV CCPS, for different values of the reference current I_REF: a 40 μW ≤ P_L ≤ 100 μW, V_REF= 50 mV, b 0.2 mW ≤ P_L ≤ 1 mW, V_REF= 100 mV and c 5 mW ≤ P_L ≤ 30 mW, V_REF= 100 mV

Fig. 6

Relative errors E_R of the generated power P_L versus load resistance R_L shown in Fig. 5(a)–(c), for the HV CCPS

The resistive load R_L in the pulse mode operation has been used for the stability test of the proposed HV CCPS. The resistive load R_L is designed by using the 1.58 kΩ resistor connected in parallel to the 0.392 kΩ resistor via the bilateral CMOS switch 4066BC, Fig. 7(a). The control voltage of the bilateral CMOS switch determines the load resistance R_L. When the switch S is turned-off, the load resistance is R_L = R_LH = 1.58 kΩ. When the switch S is turned-on, the load resistance is R_L = R_LL = 0.387 kΩ, taking into account an on-resistance of the single switch of nearly 120 Ω at a single supply of 10 V. The difference of the load resistances is ΔR_L = R_LH − R_LL = 1.193 kΩ, which presents 85% of the whole load resistance range from 0.28 to 1.68 kΩ. The common-mode load resistance is R_L = (R_LH + R_LL)/2 = 0.984 kΩ, which is nearly equal to the middle value (0.98 kΩ) of the whole load resistance range from 0.28 to 1.68 kΩ. The voltage across the resistive load R_L, caused by a DC test current I_TEST of 1 mA, has been recorded by a LeCroy WR204Xi oscilloscope. These data divided by the value of the test currents I_TEST result in a load resistance R_L in pulse mode operation. The measured transient response of changes of the load resistance R_L is shown in Fig. 7(b).

Fig. 7

The resistive load R_L in the pulse mode operation used in the stability test of the proposed HV CCPS: a circuit schematic with the measurement set-up and b measured transient response of the resistive load used in the HV CCPS

Measured transient responses of the resistive load voltage V_L of the proposed HV CCPS are shown in Fig. 8. Three different values of the generated power have been used, P_L ∈ {5 mW, 15 mW, 30 mW}. The pulse mode operation of the resistive load R_L shown in Fig. 7 has been used. The switching frequency f of the load resistance R_L is f = 20 kHz. There are no oscillations in the resistive load voltage V_L transient responses and this confirms the predictions of the stability analysis. The overshoots in Fig. 8 are the consequence of the presence of the parasitic elements at both of the terminals of the resistive load R_L mentioned in the introduction part of this section. The rise time t_r and the fall time t_f of the HV CCPS, for the resistive load voltage V_L shown in Fig. 8, are the following: t_r = 0.48 μs, t_f = 0.17 μs (P_L = 5 mW); t_r = 0.95 μs, t_f = 0.36 μs (P_L = 15 mW); t_r = 1.45 μs, t_f = 0.65 μs (P_L = 30 mW). The frequency bandwidth f_-3dB of the proposed HV CCPS for the resistive load R_L shown in Fig. 7 can be estimated as follows: f_−3dB = 0.35/t_r = 729.2 kHz (P_L = 5 mW), f_−3dB = 0.35/t_r = 368.4 kHz (P_L = 15 mW), and f_−3dB = 0.35/t_r = 241.4 kHz (P_L = 30 mW). The frequency bandwidth f_−3dB of the HV CCPS for the generated power P_L = 15 mW is 16.2 times larger than that in [15], for the same generated power.

Fig. 8

Measured transient responses of the resistive load voltage V_L of the proposed HV CCPS, for the pulse mode operation of the resistive load R_L shown in Fig. 7, and for different values of generated power P_L∈{5 mW, 15 mW, 30 mW}

Measured generated power P_L versus load resistance R_L of the proposed HV CCPS with the temperature as a parameter, 0 °C ≤ T ≤ 51 °C, with the corresponding relative errors, are shown in Fig. 9, for the generated power P_L = 10 mW and for the load resistance range 0.28 kΩ < R_L < 1.68 kΩ. The reference value of the generated power P_L has been adjusted first. This reference value corresponds to the middle of the load resistance ranges, R_L = 0.98 kΩ, at the temperature T = 25 °C. Next, the temperature has been set down to 0 °C, and after the temperature stability had been achieved, the measurements of the generated power P_L have been measured for different values of the load resistances R_L. After that, the temperature has been increased in a step of 17 °C (T ∈ {0 °C, 17 °C, 34 °C, 51 °C}), and the measurements have been repeated. The relative errors E_R are calculated related to the reference value of the generated power P_L. The relative errors E_R of the HV CCPS for the generated power P_L = 10 mW, for the load resistance range 0.28 kΩ < R_L < 1.68 kΩ, in the temperature range 0⁰ C ≤ T ≤ 51⁰ C, are -2.6% < E_R < 2.8%. As a comparison, the CCPS [7] exhibits an increase of the generated power of approximately 12% from the value of 25 mW with the increase of the temperature from 20 to 50 °C, and for the load resistance range 60 Ω < R_L < 140 Ω.

Fig. 9

Measured generated power P_L versus load resistance R_L of the proposed HV CCPS, with the temperature as a parameter, 0 °C ≤ T ≤ 51 °C, with the corresponding relative errors, for P_L = 10 mW and 0.28 kΩ < R_L < 1.68 kΩ

A figure of merit FOM [15] defined as follows

$$ FOM = \frac{{P_{L\hbox{max} } }}{{P_{L\hbox{min} } }} \cdot \frac{{R_{L\hbox{max} } }}{{R_{L\hbox{min} } }} \cdot \frac{{V_{L\hbox{max} } - V_{L\hbox{min} } }}{{V_{DD} - V_{SS} }} \cdot \frac{1}{{\left| {E_{R} \left[ \% \right]} \right|_{\hbox{max} } }} = \frac{{V_{L\hbox{max} }^{2} }}{{V_{L\hbox{min} }^{2} }} \cdot \frac{{V_{L\hbox{max} } - V_{L\hbox{min} } }}{{V_{DD} - V_{SS} }} \cdot \frac{1}{{\left| {E_{R} \left[ \% \right]} \right|_{\hbox{max} } }} $$

(32)

for the proposed HV CCPS results in FOM = 1750, which is the highest FOM achieved in CMOS technology so far. Also, the achieved FOM is nearly equal to that achieved in the CCPS based on the BJT translinear loop [3,4,5] (assuming that |E_R|_max = 2% has been achieved in [3,4,5]).

To prove that the HV CCPS is not much influenced by process parameters variations, Monte Carlo postlayout simulations have been performed using CADENCE software tools. The generated powers P_L ∈ {10 mW, 20 mW, 30 mW} for the load resistance R_L = 0.98 kΩ were simulated with 200 runs. Monte Carlo postlayout simulation results are summarised in Table 2. One can see that 67.5% of the generated powers P_L fall into P_Lavg ± σ range, between 95 and 95.5% of the generated powers P_L fall into P_Lavg ± 2σ range, and 99.5% of the generated powers P_L fall into P_Lavg ± 3σ range. Here, P_Lavg is the mean value of the generated power P_L, and σ is the standard deviation. The distribution of the generated power P_L = 30 mW obtained by the Monte Carlo postlayout simulations is shown in Fig. 10.

Table 2 Monte Carlo postlayout simulation results for HV CCPS

Fig. 10

Distribution of the generated power obtained by the Monte Carlo postlayout simulations with 200 runs of the proposed HV CCPS for P_L = 30 mW and R_L = 0.98 kΩ

6.2 Measured and simulated results for LV CCPS

The following supply, biasing, reference, and control voltages have been used for the LV CCPS: V_DD = 3.6 V, V_B1 = 0.6 V, V_B2 = V_B5 = 0.8 V, V_B3 = V_B6 = 1.4 V, V_B4 = 2.4 V, V_B7 = 1.39 V, V_REF ∈ {100 mV, 150 mV}, and 2 mV < V_C < 410 mV. The estimated equivalent transconductance parameters β₁ and β₂ of M₁ and M₂ are β₁ = β₂ ≈ 120 mA/V². The variable resistive load R_L with the resistance range 51 Ω < R_L < 201 Ω is put outside the chip. The resistances of the resistors used inside the chip are the following: R₁ = R₃ = R₄ = R₅ = R₆ = 20 kΩ, R₂ = 0.4 kΩ and R₇ = 0.5 kΩ. The value of the coefficient k_R12 is calculated as k_R12 = 0.0196. For the load resistance range mentioned above, for the generated power range 60 μW < P_L < 25 mW, assuming that V_REF = 100 mV, the parameters determining the poles ω_p1 (25) and ω_p2 (26) range as follows: 0.043 < r_ds1/(r_ds1 + R_L) < 0.644, and 0.012 < g_m2r_ds2 < 0.047. The resistor R₇ is designed by using two resistors R_7A and R_7B coupled together in series, with the resistance R₇ = R_7A + R_7B. The resistor R_7A is made by using an N +HRES polysilicon resistor with a typical value of the linear temperature coefficient (∂R_7A/∂T)/R_7A = − 2.9∙10⁻³/K, while the resistor R_7B is made by using an N-well resistor with a typical value of the linear temperature coefficient (∂R_7B/∂T)/R_7B = + 3.9∙10⁻³/K. So, the resistances of the composite resistor R₇ are the following: R_7A ≈ 290 Ω (14) and R_7B ≈ 210 Ω (15). The capacitors C_C1 and C_C2 used for the frequency compensation of OA₂ have the capacitances C_C1 = C_C2 = 5 pF. The typical absolute values of the threshold voltages V_tn and |V_tp| of the n-channel and p-channel MOSFETs are the following: V_tn ≈ 0.6 V and |V_tp| ≈ 0.74 V. All n-channel MOSFETs and all p-channel MOSFETs have drain-to-source (source-to-drain) breakdown voltages of 3.6 V, with absolute maximum of 5 V.

The post-layout simulations of the offset voltage of OA₁ in the non-inverting amplifier configuration within the LV CCPS are shown in Fig. 11. The simulations have been performed by using CADENCE software tools. The load resistance R_L of the resistive load in the feedback branch of OA₁ has been changed in the range 50 Ω ≤ R_L ≤ 200 Ω. The voltage reference V_REF = 100 mV is connected to the non-inverting input of OA₁. In addition to the resistive load R_L, there are also bond-wire inductors with inductances L_BW1 = L_BW2 = 3 nH, the capacitors of the printed circuit board and oscilloscope probes with capacitances C_PCB1 = C_PCB2 = 10 pF, and the channel resistance R_DS1 = 11.2 Ω (corresponding to R_L = 125 Ω and P_L = 10 mW) as well as the resistive voltage divider R₁-R₂, with R₁ = 20 kΩ and R₂ = 0.4 kΩ. In order to prove that the proposed design allows wide ranges of the DC biasing voltages V_B2 = V_B5 and V_B4 (the most critical from the standpoint of the ranges of the DC biasing voltages), two types of simulations have been performed. First, the DC biasing voltage V_B2 has been used as a parameter, 0.8 V ≤ V_B2 ≤ 1.8 V, with a step of ΔV_B2 = 0.1 V, while the DC biasing voltage V_B4 has been kept constant, V_B4 = 2 V. Second, the DC biasing voltage V_B2 has been kept constant, V_B2 = 1.3 V, while the DC biasing voltage V_B4 has been used as a parameter, 1.5 V ≤ V_B4 ≤ 2.5 V, with a step of ΔV_B4 = 0.1 V. These simulated results confirm that the DC biasing voltage V_B2 = V_B5 can range from 0.8 to 1.8 V (1.3 V ± 0.5 V) and that the DC biasing voltage V_B4 can range from 1.5 to 2.5 V (2 V ± 0.5 V) in the LV CCPS without any significant consequences for the generated power of P_L = 10 mW in the whole load resistance range 50 Ω ≤ R_L ≤ 200 Ω. Similar simulated results have been achieved for different generated powers P_L, as well as for OA₂.

Fig. 11

Simulated offset voltage of the operational amplifier OA₁ for V_REF = 100 mV, P_L = 10 mW, and 50 Ω ≤ R_L ≤ 200 Ω: a 0.8 V ≤ V_B2 ≤ 1.8 V, with a step of ΔV_B2 = 0.1 V, V_B4 = 2 V and b V_B2 = 1.3 V, 1.5 V ≤ V_B4 ≤ 2.5 V, with a step of ΔV_B4 = 0.1 V

Measured generated power P_L versus load resistance R_L of the proposed CCPS, for different values of the reference current I_REF, and for the fixed values of the reference voltage V_REF, are shown in Fig. 12(a)–(c). While the load resistance R_L has been changed from 51 to 201 Ω in steps of 15 Ω, the generated power P_L has been kept constant. The relative errors E_R of the generated power P_L versus load resistance R_L shown in Fig. 13 are calculated corresponding to the generated power P_L measured for the middle of the load resistance range, i.e., for R_L = 126 Ω. For the LV CCPS the relative error E_R increases for the generated power P_L < 100 μW. The largest relative errors E_R = 1.8% and E_R = − 1.8% occur for the generated powers P_L = 60 μW and P_L = 80 μW, respectively. In this way, the predictions of the analysis performed in the Sect. 5 Error analysis have been confirmed. For the LV CCPS the generated power dynamic range is P_Lmax/P_Lmin = 416.7 (52.4 dB) for the load resistance dynamic range R_Lmax/R_Lmin = 4 (12 dB).

Fig. 12

Measured generated power P_L versus load resistance R_L of the proposed LV CCPS, for different values of the reference current I_REF: a 60 μW ≤ P_L ≤ 100 μW, V_REF= 100 mV, b 0.2 mW ≤ P_L ≤ 1 mW, V_REF= 100 mV and c 5 mW ≤ P_L ≤ 25 mW, V_REF∈{100 mV, 150 mV}

Fig. 13

Relative errors E_R of the generated power P_L versus load resistance R_L shown in Fig. 12(a)–(c), for the LV CCPS

The resistive load R_L in the pulse mode operation has been used for the stability test of the proposed LV CCPS. The resistive load R_L is designed by using the 180 Ω resistor connected in parallel to the 68 Ω resistor via four bilateral CMOS switches 4066BC connected in parallel, Fig. 14(a).The control voltage of the bilateral CMOS switch determines the load resistance R_L. When the switch S is turned-off, the load resistance is R_L = R_LH = 180 Ω. When the switch S is turned-on, the load resistance is 65 Ω < R_L = R_LL < 75 Ω, taking into account an on-resistance of the single switch of nearly 120 Ω at a single supply of 10 V. The difference of the load resistances is ΔR_L = R_LH − R_LL ≈ 110 Ω, which presents 75% of the whole load resistance range from 50 to 200 Ω. The common-mode load resistance is R_L = (R_LH + R_LL)/2 ≈ 125 Ω, which is equal to the middle value of the whole load resistance range from 50 to 200 Ω. The voltages across the resistive load R_L, caused by DC test currents I_TEST of 1 mA, 10 mA, and 20 mA, have been recorded by a LeCroy WR204Xi oscilloscope. These data divided by the values of the test currents I_TEST result in a load resistance R_L in pulse mode operation. Due to both small and large resistive load currents I_L (550 μA ≤ I_L ≤ 22.4 mA for 60 μW ≤ P_L ≤ 25 mW and 50 Ω ≤ R_L ≤ 200 Ω), three different test currents I_TEST have been used. Large differences between these test currents cause different resistances of the bilateral CMOS switches 4066BC. Consequently, the load resistances R_LL are also different for different test currents I_TEST. The measured transient response of changes of the load resistance R_L is shown in Fig. 14(b).

Fig. 14

The resistive load R_L in the pulse mode operation used in the stability test of the proposed LV CCPS: a circuit schematic with the measurement set-up and b measured transient response of the resistive load used in the LV CCPS

Measured transient responses of the resistive load voltage V_L of the proposed LV CCPS are shown in Fig. 15. Three different values of the generated power have been used, P_L ∈ {1 mW, 10 mW, 25 mW}. The pulse mode operation of the resistive load R_L shown in Fig. 14 has been used. The switching frequency f of the load resistance R_L is f = 2 kHz. There are no oscillations in the resistive load voltage V_L transient responses and this confirms the predictions of the stability analysis. The overshoots in Fig. 15 are the consequence of the presence of the parasitic elements at both of the terminals of the resistive load R_L mentioned in the introduction part of this section. The rise time t_r and the fall time t_f of the LV CCPS, for the resistive load voltage V_L shown in Fig. 15, are the following: t_r = 2 μs, t_f = 2 μs (P_L = 1 mW); t_r = 3.5 μs, t_f = 4.5 μs (P_L = 10 mW); t_r = 4.5 μs, t_f = 6 μs (P_L = 25 mW). The frequency bandwidth f_−3dB of the proposed LV CCPS for the resistive load R_L shown in Fig. 14 can be estimated as follows: f_−3dB = 0.35/t_r = 175 kHz (P_L = 1 mW), f_−3dB = 0.35/t_f = 77.8 kHz (P_L = 10 mW), and f_−3dB = 0.35/t_f = 58.3 kHz (P_L = 25 mW).

Fig. 15

Measured transient responses of the resistive load voltage V_L of the proposed LV CCPS, for the pulse mode operation of the resistive load R_L shown in Fig. 14, and for different values of generated power P_L∈{1 mW, 10 mW, 25 mW}

Measured generated power P_L versus load resistance R_L of the proposed LV CCPS with the temperature as a parameter, 0 °C ≤ T ≤ 51 °C, with the corresponding relative errors, are shown in Fig. 16, for the generated power P_L = 1 mW and for the load resistance range 51 Ω < R_L < 201 Ω. The reference value of the generated power P_L has been adjusted first. This reference value correspond to the middle of the load resistance range, R_L = 126 Ω, at the temperature T = 25 °C. Next, the temperature has been set down to 0 °C, and after the temperature stability had been achieved, the measurements of the generated power P_L have been measured for different values of the load resistances R_L. After that, the temperature has been increased in a step of 17 °C (T ∈ {0 °C, 17 °C, 34 °C, 51 °C}), and the measurements have been repeated. The relative errors E_R are calculated related to the reference value of the generated power P_L. The relative errors E_R of the LV CCPS for the generated power P_L = 1 mW, for the load resistance range 51 Ω < R_L < 201 Ω, in the temperature range 0 °C ≤ T ≤ 51 °C, are − 2.9% < E_R < 1.7%. As a comparison, the CCPS [7] exhibits an increase of the generated power of approximately 12% from the value of 25 mW with the increase of the temperature from 20 to 50 °C, and for the load resistance range 60 Ω < R_L < 140 Ω.

Fig. 16

Measured generated power P_L versus load resistance R_L of the proposed LV CCPS, with the temperature as a parameter, 0 °C ≤ T ≤ 51 °C, with the corresponding relative errors, for P_L = 1 mW, 51 Ω < R_L < 201 Ω

A figure of merit FOM (32) of the proposed LV CCPS is FOM = 565.

In order to prove that the proposed LV CCPS is not much influenced by process parameters variations, Monte Carlo postlayout simulations have been performed using CADENCE software tools. The generated powers P_L ∈ {5 mW, 15 mW, 25 mW} for the load resistance R_L = 125 Ω were simulated with 200 runs. Monte Carlo postlayout simulation results are summarised in Table 3. It can be seen that between 68 and 68.8% of the generated powers P_L fall into P_Lavg ± σ range, between 94.5 and 95.5% of the generated powers P_L fall into P_Lavg ± 2σ range, and 99.5% of the generated powers P_L fall into P_Lavg ± 3σ range. Here, P_Lavg is the mean value of the generated power P_L, and σ is the standard deviation. The distribution of the generated power P_L = 25 mW obtained by the Monte Carlo postlayout simulations is shown in Fig. 17.

Table 3 Monte Carlo postlayout simulation results for LV CCPS

Fig. 17

Distribution of the generated power obtained by the Monte Carlo postlayout simulations with 200 runs of the proposed LV CCPS for P_L = 25 mW and R_L = 125 Ω

7 Conclusion

The proposed controllable constant power source in 0.35 μm CMOS technology is intended for the implementation in thermal-based sensors with variable resistance. The unconditional stability is achieved by a simple feedback design. The controllability of the generated power can be performed either by varying a reference voltage or by varying a reference current. In addition to a small relative error, the proposed high-voltage design of the controllable constant power source with a single supply of 10 V has so far the largest generated power dynamic range and the largest load resistance dynamic range among existing CMOS controllable constant-power sources. These features of the high-voltage design together with the performances of the low-voltage design with a single supply of 3.6 V confirm that the proposed controllable constant power source can be implemented in both high voltage and standard low voltage CMOS technologies.

Appendix derivation of the temperature coefficients of the offset voltages

The offset voltage V_OFFOA2 of OA₂ and its temperature coefficient ∂V_OFFOA2/∂T will be derived in this appendix. The derivations of the offset voltage V_OFFOA1 of OA₁ and its temperature coefficient ∂V_OFFOA1/∂T are similar to those of OA₂. The derivations of the offset voltage V_OFFCCI of the voltage follower part of the CCI and its temperature coefficient ∂V_OFFCCI/∂T are similar to those of the differential pair M₁₅–M₁₆ within OA₂.

The offset voltage V_OFFOA2 of OA₂ is presented by the difference of the input voltages V_G24 and V_G25 of OA₂, Fig. 1, required to drive the output voltage of OA₂ to the value V_OUT2 = V_DD − V_SG19

$$ V_{OFFOA2} = V_{G24} - V_{G25} = V_{SG25} - V_{GS16} + V_{GS15} - V_{SG24} = V_{OFFSF2} + V_{OFFDA2} $$

(33)

where V_GS15 and V_GS16 are the gate-to-source voltages of M₁₅ and M₁₆, respectively, V_SG24 and V_SG25 are the source-to-gate voltages of M₂₄ and M₂₅, respectively. So, the offset voltage V_OFFOA2 of OA₂ consists of two parts: the offset voltage V_OFFSF2 caused by the imperfections of the source followers made by M₂₄ and M₂₅ given by

$$ V_{OFFSF2} = V_{SG25} - V_{SG24} $$

(34)

and the offset voltage V_OFFDA2 caused by the imperfections of the differential pair M₁₅–M₁₆ expressed as

$$ V_{OFFDA2} = V_{GS15} - V_{GS16} $$

(35)

Consequently, the temperature coefficient ∂V_OFFOA2/∂T of the offset voltage of OA₂ can be calculated as follows

$$ \frac{{\partial V_{OFFOA2} }}{\partial T} = \frac{{\partial V_{OFFSF2} }}{\partial T} + \frac{{\partial V_{OFFDA2} }}{\partial T} $$

(36)

Assuming a simple quadratic model of saturated MOSFET [18,19,20] and neglecting the channel length modulation, the drain currents I_D24 and I_D25 of M₂₄ and M₂₅, respectively, are given by

$$ I_{D24} = \frac{1}{2}\beta_{24} \left( {V_{SG24} + V_{t24} } \right)^{2} = \frac{{V_{B6} - V_{SG24} - V_{G24} }}{{R_{5} }} $$

(37)

$$ I_{D25} = \frac{1}{2}\beta_{25} \left( {V_{SG25} + V_{t25} } \right)^{2} = \frac{{V_{B7} - V_{SG25} - V_{G25} }}{{R_{6} }} $$

(38)

The following expressions for the source-to-gate voltages V_SG24 and V_SG25 of M₂₄ and M₂₅, respectively, are obtained by solving the quadratic Eqs. (37) and (38)

$$ V_{SG24} \approx - V_{t24} + \sqrt {2\frac{{V_{B6} + V_{t24} }}{{\beta_{24} R_{5} }}} $$

(39)

$$ V_{SG25} \approx - V_{t25} + \sqrt {2\frac{{V_{B7} + V_{t25} }}{{\beta_{25} R_{6} }}} $$

(40)

The relation (39) have been derived assuming β₂₄R₅|V_t24| ≫ 1, V_B6 + V_t24 ≫ V_G24, and 2β₂₄R₅(V_B6 + V_t24) ≫ 1 (β₂₄ ≈ 0.5 mA/V², R₅ = 20 kΩ, V_t24 = − 1.35 V, V_B6 = 3.2 V, V_G24 < 100 mV for the HV CCPS, and β₂₄ ≈ 30 mA/V², R₅ = 20 kΩ, V_t24 = − 0.74 V, V_B6 = 1.4 V, V_G24 < 50 mV for the LV CCPS). The relation (40) have been derived assuming β₂₅R₆|V_t25| ≫ 1, V_B7 + V_t25 ≫ V_G25, and 2β₂₅R₆(V_B7 + V_t25) ≫ 1 (β₂₅ ≈ 0.5 mA/V², R₆ = 20 kΩ, V_t25 = − 1.35 V, V_B7 = 3.15 V, V_G24 < 100 mV for the HV CCPS, and β₂₅ ≈ 30 mA/V², R₆ = 20 kΩ, V_t25 = − 0.74 V, V_B7 = 1.39 V, V_G25 < 50 mV for the LV CCPS). Using (34), (39), and (40) the following expression can be derived for the offset voltage V_OFFSF2 caused by the imperfections of the source followers made by M₂₄ and M₂₅

$$ V_{OFFSF2} = V_{SG25} - V_{SG24} = V_{t24} - V_{t25} + \sqrt 2 \frac{{\sqrt {\left( {V_{B7} + V_{t25} } \right)\beta_{24} R_{5} } - \sqrt {\left( {V_{B6} + V_{t24} } \right)\beta_{25} R_{6} } }}{{\sqrt {\beta_{24} \beta_{25} R_{5} R_{6} } }} $$

(41)

Using the following substitutions: ΔV_t2425 = V_t24 − V_t25, V_t2425 = (V_t24 + V_t25)/2, Δβ₂₄₂₅ = β₂₄ − β₂₅, β₂₄₂₅ = (β₂₄ + β₂₅)/2, ΔR₅₆ = R₅ − R₆, R₅₆ = (R₅ + R₆)/2, ΔV_B67 = V_B6 − V_B7, V_B67 = (V_B6 + V_B7)/2, the relation (41) is transformed into the following form

$$ V_{OFFSF2} \approx \Delta V_{t2425} + \sqrt {\frac{{V_{B67} + V_{t2425} }}{{2\beta_{2425} R_{56} }}} \left( {\frac{{\Delta \beta_{2425} }}{{\beta_{2425} }} + \frac{{\Delta R_{56} }}{{R_{56} }} - \frac{{\Delta V_{B67} + \Delta V_{t2425} }}{{V_{B67} + V_{t2425} }}} \right) $$

(42)

The relation (42) have been derived using the following approximation: (1 + x)^1/2 ≈ 1 + x/2, for x ≪ 1. The temperature coefficient the offset voltage V_OFFSF2 (42) caused by the imperfections of the source followers made by M₂₄ and M₂₅ can be calculates as follows:

$$ \frac{{\partial V_{OFFSF2} }}{\partial T} \approx \frac{1}{2}\sqrt {\frac{{V_{B67} + V_{t2425} }}{{2\beta_{2425} R_{56} }}} \left( {\frac{{\Delta \beta_{2425} }}{{\beta_{2425} }} + \frac{{\Delta R_{56} }}{{R_{56} }} - \frac{{\Delta V_{B67} + \Delta V_{t2425} }}{{V_{B67} + V_{t2425} }}} \right) \cdot \left[ {\frac{1}{{V_{B67} + V_{t2425} }}\frac{{\partial \left( {V_{B67} + V_{t2425} } \right)}}{\partial T} - \frac{1}{{\beta_{2425} }}\frac{{\partial \beta_{2425} }}{\partial T} - \frac{1}{{R_{56} }}\frac{{\partial R_{56} }}{\partial T}} \right] $$

(43)

Using (42), the relation (43) becomes

$$ \frac{{\partial V_{OFFSF2} }}{\partial T} \approx \frac{1}{2}\left( {V_{OFFSF2} - \Delta V_{t2425} } \right)\left[ {\frac{1}{{V_{B67} + V_{t2425} }}\frac{{\partial \left( {V_{B67} + V_{t2425} } \right)}}{\partial T} - \frac{1}{{\beta_{2425} }}\frac{{\partial \beta_{2425} }}{\partial T} - \frac{1}{{R_{56} }}\frac{{\partial R_{56} }}{\partial T}} \right] $$

(44)

The derivation of the offset voltage V_OFFDA2 caused by the imperfections of the differential pair M₁₅–M₁₆ is similar to that in [20]. However, because the channel length modulation of M₁₅, M₁₆, M₁₉, and M₂₀ can be neglected thanks to the telescopic design, this derivation is slightly different compared to [20], where a differential pair with simple current mirror load is discussed.

With sufficiently small biasing voltage V_B2 = V_B5, drain-to-source voltages V_DS15 and V_DS16 of M₁₅ and M₁₆, respectively, are small enough to neglect the influence of the channel length modulation in these MOSFETs. So, assuming a simple quadratic model, the gate-to-source voltages V_GS15 and V_GS16 of M₁₅ and M₁₆, respectively, are given by

$$ V_{GS15} \approx \sqrt {\frac{{2I_{D15} }}{{\beta_{15} }}} + V_{t15} $$

(45)

$$ V_{GS15} \approx \sqrt {\frac{{2I_{D15} }}{{\beta_{15} }}} + V_{t15} $$

(46)

Using (35), (45), and (46) the following expression can be derived for the offset voltage V_OFFDA2 caused by the imperfections of the differential pair M₁₅–M₁₆

$$ V_{OFFDA2} = V_{GS15} - V_{GS16} = V_{t15} - V_{t16} + \sqrt 2 \frac{{\sqrt {\beta_{16} I_{D15} } - \sqrt {\beta_{15} I_{D16} } }}{{\sqrt {\beta_{15} \beta_{16} } }} $$

(47)

Using the following substitutions: ΔV_t1516 = V_t15 − V_t16, Δβ₁₅₁₆ = β₁₅ − β₁₆, β₁₅₁₆ = (β₁₅ + β₁₆)/2, ΔΙ_D1516 = I_D15 − I_D16, I_D1516 = (I_D15 + I_D16)/2, the relation (47) is transformed into the following form

$$ V_{OFFDA2} \approx \Delta V_{t1516} + \sqrt {\frac{{I_{D1516} }}{{2\beta_{1516} }}} \left( {\frac{{\Delta I_{D1516} }}{{I_{D1516} }} - \frac{{\Delta \beta_{1516} }}{{\beta_{1516} }}} \right) $$

(48)

The relation (48) have been derived using the following approximation: (1 + x)^1/2 ≈ 1 + x/2, for x ≪ 1. With sufficiently large biasing voltage V_B4, source-to-drain voltages V_SD19 and V_SD20 of M₁₉ and M₂₀, respectively, are small enough to neglect the influence of the channel length modulation in these MOSFETs. So, assuming a simple quadratic model, the source-to-gate voltages V_SG19 and V_SG20 of M₁₉ and M₂₀, respectively, are given by

$$ V_{SG19} \approx \sqrt {\frac{{2I_{D19} }}{{\beta_{19} }}} - V_{t19} $$

(49)

$$ V_{SG20} \approx \sqrt {\frac{{2I_{D20} }}{{\beta_{20} }}} - V_{t20} $$

(50)

Because V_SG19 = V_SG20, the following relation can be derived using (49) and (50)

$$ V_{t19} - V_{t20} \approx \sqrt 2 \frac{{\sqrt {\beta_{20} I_{D19} } - \sqrt {\beta_{19} I_{D20} } }}{{\sqrt {\beta_{19} \beta_{20} } }} $$

(51)

Using the following substitutions: ΔV_t1920 = V_t19 − V_t20, Δβ₁₉₂₀ = β₁₉ − β₂₀, β₁₉₂₀ = (β₁₉ + β₂₀)/2, ΔΙ_D1920 = I_D19 − I_D20, I_D1920 = (I_D19 + I_D20)/2, the relation (51) is transformed into the following form

$$ \Delta V_{t1920} \approx \sqrt {\frac{{I_{D1920} }}{{2\beta_{1920} }}} \left( {\frac{{\Delta I_{D1920} }}{{I_{D1920} }} - \frac{{\Delta \beta_{1920} }}{{\beta_{1920} }}} \right) $$

(52)

The relation (52) have been derived using the following approximation: (1 + x)^1/2 ≈ 1 + x/2, for x ≪ 1. Taking into account the fact that the drain currents of M₁₅ and M₁₉ are equal, I_D15 = I_D19, and that the drain currents of M₁₆ and M₂₀ are equal, I_D16 = I_D20, the following equalities are valid: ΔI_D1516 = ΔI_D1920, I_D1516 = I_D1920. Hence, the following expression can be derived from the relation (52)

$$ \frac{{\Delta I_{D1516} }}{{I_{D1516} }} = \frac{{\Delta I_{D1920} }}{{I_{D1920} }} \approx \frac{{\Delta \beta_{1920} }}{{\beta_{1920} }} + \sqrt {\frac{{2\beta_{1920} }}{{I_{D1920} }}} \Delta V_{t1920} $$

(53)

The offset voltage V_OFFDA2 caused by the imperfections of the differential pair M₁₅–M₁₆ is obtained using (48) and (53)

$$ V_{OFFDA2} \approx \Delta V_{t1516} + \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \Delta V_{t1920} + \sqrt {\frac{{I_{D1516} }}{{2\beta_{1516} }}} \left( {\frac{{\Delta \beta_{1920} }}{{\beta_{1920} }} - \frac{{\Delta \beta_{1516} }}{{\beta_{1516} }}} \right) $$

(54)

The temperature coefficient the offset voltage V_OFFDA2 (54) caused by the imperfections of the differential pair M₁₅–M₁₆ can be calculates as follows:

$$ \begin{aligned} \frac{{\partial V_{OFFDA2} }}{\partial T} & \approx \frac{1}{2}\Delta V_{t1920} \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \left( {\frac{1}{{\beta_{1920} }}\frac{{\partial \beta_{1920} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ & \quad + \frac{1}{2}\left( {\frac{{\Delta \beta_{1920} }}{{\beta_{1920} }} - \frac{{\Delta \beta_{1516} }}{{\beta_{1516} }}} \right)\sqrt {\frac{{I_{D1516} }}{{2\beta_{1516} }}} \left( {\frac{1}{{I_{D1516} }}\frac{{\partial I_{1516} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ \end{aligned} $$

(55)

Using (54), the relation (55) becomes

$$ \begin{aligned} \frac{{\partial V_{OFFDA2} }}{\partial T} & \approx \frac{1}{2}\Delta V_{t1920} \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \left( {\frac{1}{{\beta_{1920} }}\frac{{\partial \beta_{1920} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ & \quad + \frac{1}{2}\left( {V_{OFFDA2} - \Delta V_{t1516} - \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \Delta V_{t1920} } \right)\left( {\frac{1}{{I_{D1516} }}\frac{{\partial I_{1516} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ \end{aligned} $$

(56)

Finally, the temperature coefficient ∂V_OFFOA2/∂T = ∂V_OFFSF2/∂T + ∂V_OFFSDA2/∂T of the offset voltage of OA₂ is obtained using the relations (36), (44), and (56)

$$ \begin{aligned} \frac{{\partial V_{OFFOA2} }}{\partial T} & \approx \frac{1}{2}\left( {V_{OFFSF2} - \Delta V_{t2425} } \right)\left[ {\frac{1}{{V_{B67} + V_{t2425} }}\frac{{\partial \left( {V_{B67} + V_{t2425} } \right)}}{\partial T} - \frac{1}{{\beta_{2425} }}\frac{{\partial \beta_{2425} }}{\partial T} - \frac{1}{{R_{56} }}\frac{{\partial R_{56} }}{\partial T}} \right] \\ & \quad + \frac{1}{2}\Delta V_{t1920} \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \left( {\frac{1}{{\beta_{1920} }}\frac{{\partial \beta_{1920} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ & \quad + \frac{1}{2}\left( {V_{OFFDA2} - \Delta V_{t1516} - \sqrt {\frac{{\beta_{1920} }}{{\beta_{1516} }}} \Delta V_{t1920} } \right)\left( {\frac{1}{{I_{D1516} }}\frac{{\partial I_{D1516} }}{\partial T} - \frac{1}{{\beta_{1516} }}\frac{{\partial \beta_{1516} }}{\partial T}} \right) \\ \end{aligned} $$

(57)