A two-phase non-dominated sorting particle swarm optimization for chip feature design to improve wafer exposure effectiveness

Highlights

• A two-phase non-dominated sorting particle swarm optimization (TNSPSO) is proposed.

• Maximizing gross die number and minimizing shot number are performed simultaneously.

• Alternative chip features are provided to enhance wafer exposure effectiveness.

• An empirical study was conducted from a semiconductor company.

Abstract

Enhancing the competitive advantages of wafer fabs is crucial to increase the number of gross dies per wafer and to reduce average die cost. Most of existing studies about IC (integrated circuit) feature design focus on yield enhancement, yet little research has been done on cost reduction through increasing gross die number and decreasing shot number simultaneously. To generate the alternative feature design to improve wafer exposure effectiveness, a prediction model between chip size and gross die number and shot number was built through amount of data collection and model training. However, it’s difficult to consider different exposure conditions under various parameter setting of amount of IC features. In order to fill the gap of considering real setting, this study aims to propose a two-phase non-dominated sorting particle swarm optimization (TNSPSO) method to maximize number of gross die and minimize the shot number and then suggests alternative chip features for IC designers. First, non-dominated sorting algorithm is used to find the solutions on the frontier. Second, these particles on the frontier are diffused toward the sparse region on the frontier. To evaluate the validity of proposed approach, two conventional heuristic algorithms, non-dominated sorting genetic algorithm II (NSGA-II) and multi-objective particle swarm optimization (MOPSO) were selected . The experiment results showed that the proposed method not only capture the solutions closer to the Pareto frontier but also has better convergence and diversity of the solutions than the other methods. The proposed approach can assist IC designer in effectively deriving chip layout design with enhancement of wafer exposure effectiveness.

Introduction

Following by Moore’s Law (Moore, 1965), that the number of transistors fabricated on an integrated circuit (IC) will be approximately doubled every 12 to 24 months for capturing less cost, the semiconductor technology has strived for continuously migration and shrinking IC feature sizes. As global competition continues to strengthen in semiconductor industry, wafer fabrication has to advance manufacturing technology and improve wafer productivity for continuous cost reduction. The wafer productivity is defined as the fraction of the effective useful wafer area to the total wafer area (Chien & Hsu, 2014). The useful wafer area is denoted as the product of number of good die and die size and determined by yield rate and gross die number (Maly, 1992, Turley, 2003). Therefore, except yield improvement, increasing number of gross dies per wafer is crucial for reduction of average die cost.

Little research has been done on cost reduction through increasing the gross die number per wafer and decreasing the required shot number. Wafer fabrication presents design rules as suggestions and references for chip designer in IC design for achievement of high quality. In particular, Very Large Scale Integration (VLSI) design process can be generally partitioned into five interrelated steps: architecture design, micro-architecture design, logic design, circuit design and physic layout design (Weste & Harris, 2005). Architecture describes the functions of the system. Micro-architecture describes how the architecture is partitioned into registers and functional units. Logic describes how functional units are constructed. Circuit design describes how transistors are used to implement the logic. The circuit can be tailored to emphasize high performance or low power. Physical layout design describes the layout of the chip. In particular, the chip area and chip yield are determined by the density of components on a chip in layout design. The designer wants to make the components as small as possible and installs as many function as possible on a chip.

The IC feature design is determined to accommodate the microcircuitry of ICs for ensuring desired functionality. The IC designers would make orders and provide the information of pattern layout size and chip feature for photolithography engineers. Then, an optimal wafer exposure pattern with the maximum number of gross die and minimum shot number was selected. Iterative cutting algorithms have been developed to maximize the gross dice exposed on a wafer and minimize the number of exposure shots, subject to throughput and yield such as the flat bottom line, dummy pattern, the sharing rules of the dummy pattern, the width of the scribe line, the position of the alignment mark and the mask size (Chien et al., 1999, Chien et al., 2001). The wafer exposure layout algorithm not only reduces the operating cost by minimizing the number of exposures per wafer, but also increases the yield by maximizing the distance from good dice to the wafer edge. Moreover, the cycle time of wafer exposure has to be decreased for increasing more wafer per hour (wafer per hour) through reducing the shot number of exposure machine (i.e., stepper or scanner). That is, given the same exposable wafer space, the feature size design with higher utilization of mask field will need fewer shot number and thus result in higher WPH. The chip feature that has higher utilization of mask field may be exposed to fewer numbers of gross die than other designs with lower utilization of mask field. Therefore, it is crucial to find a better chip feature for exposing few shot number per wafer without losing number of gross die simultaneously. Although algebraic equations were developed to estimate the numbers of gross dices (de Vries, 2005, Ferris-Prabhu, 1989), the existing methods used try and error method to find the direction for improvement that cannot help IC designers to determine the exact adjustment value. Chien, Hsu, and Chang (2013) proposed a novel metric, Overall Wafer Effectiveness (OWE), to measure wafer exposure effectiveness and integrate mask-field-utilization as Mask-field-utilization weighted OWE (MOWE) to measure number of gross die and shot number simultaneously.

Indeed, finding alternative chip feature design with more number of gross die and using fewer shot number is formulated as a multi-objective optimization problem. Given the constraints including the limits of chip length, chip width, and chip area, the optimal solutions are selected by large number of gross die and small shot number. Chien and Hsu (2014) proposed a data mining method to generate specific improved regions of chip feature for IC designers to optimize the chip feature design according to MOWE which is a weighted function of these two objectives. However, it needs to build a prediction model through amount of data collection and model training. It’s difficult to consider different exposure conditions under various parameter setting of amount of IC features.

In order to bridge the gap between IC chip feature design and wafer fabrication for adopting various feature requirements, this study aims to propose a two-phase non-dominated sorting particle swarm optimization, (TNSPSO), which integrates particle swarm optimization (PSO) (Kennedy & Eberhart, 1995) and non-dominated fast sorting to determine alternative chip feature and generate specific improved regions of chip feature for IC designers to optimize the chip feature design to maximize number of gross die and minimize the shot number. Through identifying the Pareto-optimal solutions among a set of non-dominated solutions, it provides the alternative designs for increasing number of gross die and decreasing shot number simultaneously. In the first stage, the amounts of Pareto-frontier solutions are identified through PSO. In the second stage, the solutions on the Pareto-frontier are extended to fulfill the gap between solutions. To estimate the validity of the proposed approach, three different products with different chip size based on the real setting are conducted for comparisons among other multi-objective algorithms. The results showed that the proposed TNSPSO can facilitate the layout design to adjust the chip feature and improve wafer productivity without increasing extra manufacturing cost. IC designer can choose the alternatives of chip size features from a set of non-dominated solutions without building model in advance.

The reminder of this paper is organized as follows. Section 2 introduced the related works regarding the IC feature design and wafer exposure. Section 3 proposes the TNSPSO model to advice the alternative feature design from a set of non-dominated solutions. Section 4 compares the effectiveness of proposed TNSPSO by typical numerical test problems and three types of IC feature size with other multiple objective evolutionary algorithms. Finally, Section 5 concludes this study with discussion on contribution and future research directions.