Improved digital performance of charge plasma based junctionless C-FinFETs at 10 nm technology node and beyond

Abstract

This paper investigates the digital performance of novel charge plasma based complementary (CPJL) FinFET inverters in terms of low and high noise margins, logic swing LS, DC power consumption P_DC, rise t_r and fall t_f times, and propagations delay at both 10 and 7 nm technology nodes. In addition, their performance is compared with equivalent junctionless (JL) CFinFET inverters. Obtained results are physically analyzed including quantum–mechanical effects. Furthermore, the oscillation frequency of a three-stage ring oscillator constructed with CPJL-CFinFETs is computed, and compared with their JL-CFinFET counterpart. Our findings reveal that while dissipating less OFF-state power, t_r and t_f of the proposed CPJL inverter exhibit significant reduction of ~73.92% and ~79.82%, respectively, relative to its equally sized JL inverter value at 10 nm technology node. Moreover, the oscillation frequency of a three-stage ring oscillator (RO) built with CPJL inverters exhibits ~323.75% enhancement compared to its JL RO at 10 nm node.

Introduction

Aggressive down scaling of various kinds of MOSFETs built using different materials such as Si [1], [2], [3] and Ge [4], [5] leads to reduced gate control over the charge transport through the channel, which entails short channel effects (SCEs). In order to mitigate these shortcomings, the multigate architectures, especially tri-gated FinFETs, gained huge attention in the sub-30 nm technology node owing to their excellent control of short channel effects (SCEs), lower leakage current and high packing density [1], [2], [3]. For extremely miniaturized devices, the fabrication of p-n junctions having very high doping concentration gradient is critical and costly as well [6]. The junctionless (JL) FinFET featuring uniform doping type with a typical concentration ~10¹⁹ cm⁻³ [6] throughout the channel and source/drain regions has been proposed as a very promising option to address these problems [6], [7], [8], [9], [10].There have been some recent investigations concerning the impact of non uniform doping concentration on the behavior of JL FinFETs which include modeling of threshold voltage [11], evaluation of digital performance [12]and investigation of analog/RF as well as linearity performance [13] of JL FinFETs with Gaussian doping profile. Unfortunately heavily doped JL transistors are, however, prone to random dopant fluctuations (RDFs), line edge roughness (LER) and threshold voltage variability [14], [15], [16].

To alleviate the foregoing shortcomings of JL-FinFETs we propose, for the first time, a new device concept of charge plasma based junction-less FinFETs (CPJL-FinFETs). The doping concentration of Si Fin is considered to be 1 × 10¹⁷ cm⁻³ following ref. [17]. While the charge-plasma concept was conceived earlier in the context of the diode, BJT, and double gate MOS structures and the related findings were reported in [8], [17], [18], [19], [20], [21], [22], [23], there have been no such investigations towards the usefulness of charge plasma based tri-gated FinFETs for digital circuit applications.

The objective of this paper is to investigate comprehensively the digital performance of a complementary-Fin (C- Fin) inverter using CPJL-FinFETs at both 10 and 7 nm technology nodes following the guidelines noted in the International Roadmap for Devices and Systems [24], and to present a comparison with its identical JL-Fins counterpart supported by physics based analysis including quantum–mechanical effects. In addition, we construct a 3-stage ring oscillator (RO) using C-FinFET inverters and determine propagation delay per inverter stage (t_p), and also the frequency of oscillations (f_osc) of the oscillator. In order to achieve our goal, first we design an inverter using p-channel CPJL-FinFET and an n-channel CPJL-FinFET. Next, we simulate its characteristics to extract multiple digital device parameters such as noise margin (NM), logic swing (LS), DC power consumption (P_DC), rise time (t_r), fall time (t_f), and propagation delay per inverter (t_p). Finally, we compare the above-noted digital performance parameters for CPJL-Fin inverter with those of JL-Fin inverter.