Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

  • Review Article
  • Published:

Two-dimensional materials for next-generation computing technologies

Nature Nanotechnology volume 15, pages 545–557 (2020)Cite this article

Subjects

Abstract

Rapid digital technology advancement has resulted in a tremendous increase in computing tasks imposing stringent energy efficiency and area efficiency requirements on next-generation computing. To meet the growing data-driven demand, in-memory computing and transistor-based computing have emerged as potent technologies for the implementation of matrix and logic computing. However, to fulfil the future computing requirements new materials are urgently needed to complement the existing Si complementary metal–oxide–semiconductor technology and new technologies must be developed to enable further diversification of electronics and their applications. The abundance and rich variety of electronic properties of two-dimensional materials have endowed them with the potential to enhance computing energy efficiency while enabling continued device downscaling to a feature size below 5 nm. In this Review, from the perspective of matrix and logic computing, we discuss the opportunities, progress and challenges of integrating two-dimensional materials with in-memory computing and transistor-based computing technologies.

This is a preview of subscription content, access via your institution

Access options

Buy this article

  • Purchase on Springer Link
  • Instant access to full article PDF
Buy now

Prices may be subject to local taxes which are calculated during checkout

Fig. 1: Schematic illustration of matrix and logic computing.
Fig. 2: Unique characteristics of 2D materials and opportunities for next-generation computing.
Fig. 3: Dimensional scaling advantages of 2D-material-based transistors.
Fig. 4: Advantages of 2D materials for integration.
Fig. 5: Roadmap of integrating 2D materials for next-generation computing.

Similar content being viewed by others

References

  1. Horowitz, M. Computing's energy problem (and what we can do about it). In Proc. 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 10–14 (IEEE, 2014).

  2. Lee, D. U. et al. A 1.2 V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. In Proc. 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 432–433 (IEEE, 2014).

  3. Liu, D. & Park, S. Three-dimensional and 2.5 dimensional interconnection technology: state of the art. J. Electron. Packag 136, 014001 (2014).

    Google Scholar 

  4. Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74–78 (2017).

    CAS  Google Scholar 

  5. Dennard, R. H., Gaensslen, F. H., Rideout, V. L., Bassous, E. & LeBlanc, A. R. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE J. Solid-State Circuits 9, 256–268 (1974).

    Google Scholar 

  6. Irisawa, T., Numata, T., Tezuka, T., Sugiyama, N. & Takagi, S. I. Electron transport properties of ultrathin-body and tri-gate SOI nMOSFETs with biaxial and uniaxial strain. In Proc. 2006 International Electron Devices Meeting 1–4 (IEEE, 2006).

  7. Uchida, K. et al. Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm. In Proc. Technical Digest-International Electron Devices Meeting 47–50 (IEEE, 2002).

  8. Ielmini, D. & Wong, H. S. P. In-memory computing with resistive switching devices. Nat. Electron. 1, 333–343 (2018).

    Google Scholar 

  9. Borghetti, J. et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464, 873–876 (2010).

    CAS  Google Scholar 

  10. Tang, J. et al. Bridging biological and artificial neural networks with emerging neuromorphic devices: fundamentals, progress, and challenges. Adv. Mater. 31, 1902761 (2019).

    CAS  Google Scholar 

  11. Yu, S. Neuro-inspired computing with emerging nonvolatile memorys. Proc. IEEE 106, 260–285 (2018).

    CAS  Google Scholar 

  12. Burr, G. W. et al. Experimental demonstration and tolerancing of a large-scale neural network (165000 synapses) using phase-change memory as the synaptic weight element. IEEE Trans. Electron Devices 62, 3498–3507 (2015).

    Google Scholar 

  13. Merrikh-Bayat, F. et al. High-performance mixed-signal neurocomputing with nanoscale floating-gate memory cell arrays. IEEE Trans. Neural Netw. Learn. Syst. 29, 4782–4790 (2017).

    Google Scholar 

  14. Boyn, S. et al. Learning through ferroelectric domain dynamics in solid-state synapses. Nat. Commun. 8, 14736 (2017).

    CAS  Google Scholar 

  15. Yoong, H. Y. et al. Epitaxial ferroelectric Hf0.5Zr0.5O2 thin films and their implementations in memristors for brain‐inspired computing. Adv. Funct. Mater. 28, 1806037 (2018).

    Google Scholar 

  16. Mizrahi, A. et al. Neural-like computing with populations of superparamagnetic basis functions. Nat. Commun. 9, 1533 (2018).

    Google Scholar 

  17. Zhu, L. Q., Wan, C. J., Guo, L. Q., Shi, Y. & Wan, Q. Artificial synapse network on inorganic proton conductor for neuromorphic systems. Nat. Commun. 5, 3158 (2014).

    Google Scholar 

  18. van de Burgt, Y. et al. A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing. Nat. Mater. 16, 414–418 (2017).

    Google Scholar 

  19. Gerasimov, J. Y. et al. An evolvable organic electrochemical transistor for neuromorphic applications. Adv. Sci. 6, 1801339 (2019).

    Google Scholar 

  20. Fiori, G. et al. Electronics based on two-dimensional materials. Nat. Nanotechnol. 9, 768–779 (2014).

    CAS  Google Scholar 

  21. Liu, Y. et al. Van der Waals heterostructures and devices. Nat. Rev. Mater. 1, 16042 (2016).

    CAS  Google Scholar 

  22. Chhowalla, M., Jena, D. & Zhang, H. Two-dimensional semiconductors for transistors. Nat. Rev. Mater. 1, 16052 (2016).

    CAS  Google Scholar 

  23. Gibertini, M., Koperski, M., Morpurgo, A. & Novoselov, K. Magnetic 2D materials and heterostructures. Nat. Nanotechnol. 14, 408–419 (2019).

    CAS  Google Scholar 

  24. Fei, Z. et al. Ferroelectric switching of a two-dimensional metal. Nature 560, 336 (2018).

    CAS  Google Scholar 

  25. Xue, F. et al. Gate-tunable and multidirection-switchable memristive phenomena in a van der Waals ferroelectric. Adv. Mater. 31, 1901300 (2019).

    Google Scholar 

  26. Si, M. et al. A ferroelectric semiconductor field-effect transistor. Nat. Electron. 2, 580–586 (2019).

    CAS  Google Scholar 

  27. Liu, Y., Huang, Y. & Duan, X. van der Waals integration before and beyond two-dimensional materials. Nature 567, 323 (2019).

    CAS  Google Scholar 

  28. Liu, S. et al. Eliminating negative‐SET behavior by suppressing nanofilament overgrowth in cation‐based memory. Adv. Mater. 28, 10623–10629 (2016).

    CAS  Google Scholar 

  29. Wang, M. et al. Robust memristors based on layered two-dimensional materials. Nat. Electron. 1, 130 (2018).

    CAS  Google Scholar 

  30. Sun, L. et al. Self-selective van der Waals heterostructures for large scale memory array. Nat. Commun. 10, 1–7 (2019).

    Google Scholar 

  31. Shi, Y. et al. Electronic synapses made of layered two-dimensional materials. Nat. Electron. 1, 458–465 (2018).

    Google Scholar 

  32. Zhang, F. et al. Electric-field induced structural transition in vertical MoTe2- and Mo1-xWxTe2-based resistive memories. Nat. Mater. 18, 55–61 (2019).

    CAS  Google Scholar 

  33. Cheng, P., Sun, K. & Hu, Y. H. Memristive behavior and ideal memristor of 1T Phase MoS2 nanosheets. Nano Lett. 16, 572–576 (2015).

    Google Scholar 

  34. Liu, C. et al. Small footprint transistor architecture for photoswitching logic and in situ memory. Nat. Nanotechnol. 14, 662–667 (2019).

    CAS  Google Scholar 

  35. Ye, P. D. Steep-slope hysteresis-free negative-capacitance 2D transistors. Nat. Nanotechnol. 13, 24–28 (2018).

    Google Scholar 

  36. Si, M. et al. Steep-slope WSe2 negative capacitance field-effect transistor. Nano Lett. 18, 3682–3687 (2018).

    CAS  Google Scholar 

  37. Sarkar, D. et al. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature 526, 91–95 (2015).

    CAS  Google Scholar 

  38. Qiu, C. et al. Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches. Science 361, 387–392 (2018).

    CAS  Google Scholar 

  39. Wang, L. et al. Artificial synapses based on multiterminal memtransistors for neuromorphic application. Adv. Funct. Mater. 29, 1901106 (2019).

    Google Scholar 

  40. Wang, S. et al. A photoelectric-stimulated MoS2 transistor for neuromorphic engineering. Research 2019, 1618798 (2019).

    Google Scholar 

  41. Xia, Q. & Yang, J. J. Memristive crossbar arrays for brain-inspired computing. Nat. Mater. 18, 309–323 (2019).

    CAS  Google Scholar 

  42. Jackson, B. L. et al. Nanoscale electronic synapses using phase change devices. ACM J. Emerg. Technol. Comput. Syst. 9, 1–20 (2013).

    Google Scholar 

  43. Yang, C. S. et al. A synaptic transistor based on quasi-2D molybdenum oxide. Adv. Mater. 29, 1700906 (2017).

    Google Scholar 

  44. Yang, C.-S. et al. All-solid-state synaptic transistor with ultralow conductance for neuromorphic computing. Adv. Funct. Mater. 28, 1804170 (2018).

    Google Scholar 

  45. Zhu, J. et al. Ion gated synaptic transistors based on 2D van der Waals crystals with tunable diffusive dynamics. Adv. Mater. 30, 1800195 (2018).

    Google Scholar 

  46. Vu, Q. A. et al. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio. Nat. Commun. 7, 12725 (2016).

    CAS  Google Scholar 

  47. Vu, Q. A. et al. a high-on/off-ratio floating-gate memristor array on a flexible substrate via CVD-grown large-area 2D layer stacking. Adv. Mater. 29, 1703363 (2017).

    Google Scholar 

  48. Sharbati, M. T. et al. Low-power, electrochemically tunable graphene synapses for neuromorphic computing. Adv. Mater. 30, 1802353 (2018).

    Google Scholar 

  49. Ambrogio, S. et al. Equivalent-accuracy accelerated neural-network training using analogue memory. Nature 558, 60–67 (2018).

    CAS  Google Scholar 

  50. Lastras-Montaño, M. A. & Cheng, K.-T. J. N. E. Resistive random-access memory based on ratioed memristors. Nat. Electron. 1, 466–472 (2018).

    Google Scholar 

  51. Kuc, A., Zibouche, N. & Heine, T. Influence of quantum confinement on the electronic structure of the transition metal sulfide TS2. Phys. Rev. B 83, 245213 (2011).

    Google Scholar 

  52. Lee, D. et al. Multibit MoS2 photoelectronic memory with ultrahigh sensitivity. Adv. Mater. 28, 9196–9202 (2016).

    CAS  Google Scholar 

  53. Lee, J. et al. Monolayer optical memory cells based on artificial trap-mediated charge storage and release. Nat. Commun. 8, 14734 (2017).

    CAS  Google Scholar 

  54. Xiang, D. et al. Two-dimensional multibit optoelectronic memory with broadband spectrum distinction. Nat. Commun. 9, 2966 (2018).

    Google Scholar 

  55. Mennel, L. et al. Ultrafast machine vision with 2D material neural network image sensors. Nature 579, 62–66 (2020).

    CAS  Google Scholar 

  56. Sangwan, V. K. et al. Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide. Nature 554, 500–5047 (2018).

    CAS  Google Scholar 

  57. Jadwiszczak, J. et al. MoS2 memtransistors fabricated by localized helium ion beam irradiation. ACS nano 13, 14262–14273 (2019).

    CAS  Google Scholar 

  58. Huh, W. et al. Synaptic barristor based on phase‐engineered 2D heterostructures. Adv. Mater. 30, 1801447 (2018).

    Google Scholar 

  59. Midya, R. et al. Anatomy of Ag/Hafnia-based selectors with 1010 nonlinearity. Adv. Mater. 29, 1604457 (2017).

    Google Scholar 

  60. Prezioso, M. et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61–64 (2015).

    CAS  Google Scholar 

  61. Sangwan, V. et al. Neuromorphic nanoelectronic materials. Nat. Nanotechnol. https://doi.org/10.1038/s41565-020-0647-z (2020).

  62. John, R. A. et al. Synergistic gating of electro‐iono‐photoactive 2D chalcogenide neuristors: coexistence of hebbian and homeostatic synaptic metaplasticity. Adv. Mater. 30, 1800220 (2018).

    Google Scholar 

  63. Yang, J.-T. et al. Artificial synapses emulated by an electrolyte-gated tungsten-oxide transistor. Adv. Mater. 30, 1801548 (2018).

    Google Scholar 

  64. Zhu, X., Li, D., Liang, X. & Lu, W. D. Ionic modulation and ionic coupling effects in MoS2 devices for neuromorphic computing. Nat. Mater. 18, 141–148 (2019).

    CAS  Google Scholar 

  65. Wang, S. et al. A MoS2 /PTCDA hybrid heterojunction synapse with efficient photoelectric dual modulation and versatility. Adv. Mater. 31, 1806227 (2019).

    Google Scholar 

  66. Tian, H., Wang, X., Wu, F., Yang, Y. & Ren, T.-L. High performance 2D perovskite/graphene optical synapses as artificial eyes. In Proc. 2018 IEEE International Electron Devices Meeting (IEDM) 38.6.1–38.6.4 (IEEE, 2018).

  67. Seo, S. et al. Artificial optic-neural synapse for colored and color-mixed pattern recognition. Nat. Commun. 9, 5106 (2018).

    Google Scholar 

  68. Grollier, J. et al. Neuromorphic spintronics. Nat. Electron. https://doi.org/10.1038/s41928-019-0360-9 (2020).

  69. Song, T. et al. Giant tunneling magnetoresistance in spin-filter van der Waals heterostructures. Science 360, 1214–1218 (2018).

    CAS  Google Scholar 

  70. Lin, X. et al. Two-dimensional spintronics for low-power electronics. Nat. Electron. 2, 274–283 (2019).

    CAS  Google Scholar 

  71. Yan, R. H., Ourmazd, A. & Lee, K. F. Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39, 1704–1710 (1992).

    CAS  Google Scholar 

  72. Seabaugh, A. C. & Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095–2110 (2010).

    CAS  Google Scholar 

  73. Ionescu, A. M. & Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011).

    CAS  Google Scholar 

  74. Lembke, D., Allain, A. & Kis, A. Thickness-dependent mobility in two-dimensional MoS2 transistors. Nanoscale 7, 6255–6260 (2015).

    CAS  Google Scholar 

  75. Yu, Z. et al. Realization of room‐temperature phonon‐limited carrier transport in monolayer MoS2 by dielectric and carrier screening. Adv. Mater. 28, 547–552 (2016).

    CAS  Google Scholar 

  76. Fang, H. et al. High-performance single layered WSe2 p-FETs with chemically doped contacts. Nano Lett. 12, 3788–3792 (2012).

    CAS  Google Scholar 

  77. Liu, W. et al. Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors. Nano Lett. 13, 1983–1990 (2013).

    CAS  Google Scholar 

  78. Cui, Y. et al. High-performance monolayer WS2 field-effect transistors on high-κ dielectrics. Adv. Mater. 27, 5230–5234 (2015).

    CAS  Google Scholar 

  79. Liu, T. et al. Crested two-dimensional transistors. Nat. Nanotechnol. 14, 223–226 (2019).

    CAS  Google Scholar 

  80. Zhu, W., Perebeinos, V., Freitag, M. & Avouris, P. Carrier scattering, mobilities, and electrostatic potential in monolayer, bilayer, and trilayer graphene. Phys. Rev. B 80, 235402 (2009).

    Google Scholar 

  81. Banszerus, L. et al. Ultrahigh-mobility graphene devices from chemical vapor deposition on reusable copper. Sci. Adv. 1, e1500222 (2015).

    Google Scholar 

  82. Schwierz, F. Graphene transistors. Nat. Nanotechnol. 5, 487–496 (2010).

    CAS  Google Scholar 

  83. Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol. 6, 147–150 (2011).

    CAS  Google Scholar 

  84. Desai, S. B. et al. MoS2 transistors with 1-nanometer gate lengths. Science 354, 99–102 (2016).

    CAS  Google Scholar 

  85. Khan, A. I., Yeung, C. W., Chenming, H. & Salahuddin, S. Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation. In Proc. 2011 IEEE International Electron Devices Meeting (IEDM) 111.3.1.–11.3.4. (IEEE, 2011).

  86. Yu, Z. et al. Negative capacitance 2D MoS2 transistors with sub-60mV/dec subthreshold swing over 6 orders, 250 μA/μm current density, and nearly-hysteresis-free. In Proc. 2017 IEEE International Electron Devices Meeting (IEDM) 23.26.21–23.26.24 (IEEE, 2017).

  87. Muratore, C. et al. Continuous ultra-thin MoS2 films grown by low-temperature physical vapor deposition. Appl Phys. Lett. 104, 261604 (2014).

    Google Scholar 

  88. Ji, J. et al. Two-dimensional antimonene single crystals grown by van der Waals epitaxy. Nat. Commun. 7, 13352 (2016).

    CAS  Google Scholar 

  89. Li, X. et al. Large-area synthesis of high-quality and uniform graphene films on copper foils. Science 324, 1312–1314 (2009).

    CAS  Google Scholar 

  90. Liu, Y., Duan, X., Huang, Y. & Duan, X. Two-dimensional transistors beyond graphene and TMDCs. Chem. Soc. Rev. 47, 6388–6409 (2018).

    CAS  Google Scholar 

  91. Das, S., Chen, H.-Y., Penumatcha, A. V. & Appenzeller, J. High performance multilayer MoS2 transistors with scandium contacts. Nano Lett. 13, 100–105 (2012).

    Google Scholar 

  92. Kappera, R. et al. Phase-engineered low-resistance contacts for ultrathin MoS2 transistors. Nat. Mater. 13, 1128–1134 (2014).

    CAS  Google Scholar 

  93. Xia, F., Perebeinos, V., Lin, Y.-M., Wu, Y. & Avouris, P. The origins and limits of metal–graphene junction resistance. Nat. Nanotechnol. 6, 179–184 (2011).

    CAS  Google Scholar 

  94. Allain, A., Kang, J., Banerjee, K. & Kis, A. Electrical contacts to two-dimensional semiconductors. Nat. Mater. 14, 1195–1205 (2015).

    CAS  Google Scholar 

  95. Cui, X. et al. Multi-terminal transport measurements of MoS2 using a van der Waals heterostructure device platform. Nat. Nanotechnol. 10, 534–540 (2015).

    CAS  Google Scholar 

  96. Duan, X. et al. Lateral epitaxial growth of two-dimensional layered semiconductor heterojunctions. Nat. Nanotechnol. 9, 1024–1030 (2014).

    CAS  Google Scholar 

  97. Lee, G.-H. et al. Highly stable, dual-gated MoS2 transistors encapsulated by hexagonal boron nitride with gate-controllable contact, resistance, and threshold voltage. ACS nano 9, 7019–7026 (2015).

    CAS  Google Scholar 

  98. Zhao, Y. et al. Passivation of black phosphorus via self‐assembled organic monolayers by van der Waals epitaxy. Adv. Mater. 29, 1603990 (2017).

    Google Scholar 

  99. He, D. et al. High-performance black phosphorus field-effect transistors with long-term air stability. Nano Lett. 19, 331–337 (2018).

    Google Scholar 

  100. Qiu, C. et al. Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science 355, 271–276 (2017).

    CAS  Google Scholar 

  101. Li, W. et al. Uniform and ultrathin high-k gate dielectrics for two-dimensional electronic devices. Nat. Electron. 2, 563–571 (2019).

    CAS  Google Scholar 

  102. Cheng, R. et al. High-frequency self-aligned graphene transistors with transferred gate stacks. Proc. Natl Acad. Sci. USA 109, 11588–11592 (2012).

    CAS  Google Scholar 

  103. Yang, T. et al. Van der Waals epitaxial growth and optoelectronics of large-scale WSe2/SnS2 vertical bilayer p–n junctions. Nat. Commun. 8, 1906 (2017).

    Google Scholar 

  104. Xie, L., Jiao, L. & Dai, H. Selective etching of graphene edges by hydrogen plasma. J. Am. Chem. Soc. 132, 14751–14753 (2010).

    CAS  Google Scholar 

  105. Ryu, G. H. et al. Striated 2D lattice with sub‐nm 1D etch channels by controlled thermally induced phase transformations of PdSe2. Adv. Mater. 31, 1904251 (2019).

    CAS  Google Scholar 

  106. Liao, L. et al. High-speed graphene transistors with a self-aligned nanowire gate. Nature 467, 305–308 (2010).

    CAS  Google Scholar 

  107. Kang, M., Gonugondla, S. K., Patil, A. & Shanbhag, N. R. A multi-functional in-memory inference processor using a standard 6T SRAM array. IEEE J. Solid-State Circuits 53, 642–655 (2018).

    Google Scholar 

  108. Sim, J. et al. A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE system. In Proc. 2016 IEEE International Solid-State Circuits Conference (ISSCC) 264–265 (IEEE, 2016).

  109. Zhang, J., Wang, Z. & Verma, N. In-memory computation of a machine-learning classifier in a standard 6T SRAM array. IEEE J. Solid-State Circuits 52, 915–924 (2017).

    Google Scholar 

  110. Hills, G. et al. Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 595–602 (2019).

    CAS  Google Scholar 

  111. Li, L. et al. Black phosphorus field-effect transistors. Nat. Nanotechnol. 9, 372–377 (2014).

    CAS  Google Scholar 

  112. Yang, Z. et al. Field-effect transistors based on amorphous black phosphorus ultrathin films by pulsed laser deposition. Adv. Mater. 27, 3748–3754 (2015).

    CAS  Google Scholar 

  113. Avsar, A. et al. Air-stable transport in graphene-contacted, fully encapsulated ultrathin black phosphorus-based field-Effect transistors. ACS Nano 9, 4138–4145 (2015).

    CAS  Google Scholar 

  114. Xia, F. et al. Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics. Nat. Commun. 5, 4458 (2014).

    CAS  Google Scholar 

  115. Kamalakar, M. et al. Low schottky barrier black phosphorus field-effect devices with ferromagnetic tunnel contacts. Small 11, 2209–2216 (2015).

    CAS  Google Scholar 

  116. Liu, H. et al. Phosphorene: an unexplored 2D semiconductor with a high hole mobility. ACS Nano 8, 4033–4041 (2014).

    CAS  Google Scholar 

  117. Wu, J. et al. High electron mobility and quantum oscillations in non-encapsulated ultrathin semiconducting Bi2O2Se. Nat. Nanotechnol. 12, 530–534 (2017).

    CAS  Google Scholar 

  118. Lu, H. & Seabaugh, A. Tunnel field-effect transistors: state-of-the-art. IEEE J. Electron Devices Soc. 2, 44–49 (2014).

    CAS  Google Scholar 

  119. Kim, S. et al. Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches. Nat. Nanotechnol. 15, 203–206 (2020).

    CAS  Google Scholar 

  120. Knoll, L. et al. Inverters with strained Si nanowire complementary tunnel field-effect transistors. IEEE Electron Device Lett. 34, 813–815 (2013).

    CAS  Google Scholar 

  121. Ganjipour, B. et al. Tunnel field-effect transistors based on InP-GaAs heterostructure nanowires. ACS Nano 6, 3109–3113 (2012).

    CAS  Google Scholar 

  122. Gandhi, R. et al. CMOS-compatible vertical-silicon-nanowire Gate-All-Around p-type tunneling FETs with 50-mV/decade subthreshold swing. IEEE Electron Device Lett. 32, 1504–1506 (2011).

    CAS  Google Scholar 

  123. Dewey, G. et al. Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing. In. Proc. 2011 International Electron Devices Meet 33.36.31–33.36.34 (IEEE, 2011).

  124. Leonelli, D. et al. Performance enhancement in multi-gate tunneling field effect transistors by scaling the Fin-width. Jpn. J. Appl. Phys. 49, 04DC10 (2010).

    Google Scholar 

  125. Jeon, K. et al. Si tunnel transistors with a novel silicided source and 46 mV/dec swing. In Proc. 2010 Symposium VLSI Technology 121–122 (IEEE, 2010).

  126. Kim, S. et al. Germanium-source tunnel field effect transistors with record high ION/IOFF. In Proc. 2009 Symposium VLSI Technology 178–179 (IEEE, 2009).

  127. Lee, M.-H. et al. Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs. In Proc. 2016 IEEE International Electron Devices Meeting (IEDM) 12.11.11–12.11. 14 (IEEE, 2016).

  128. Jo, J. & Shin, C. Negative capacitance field effect transistor with hysteresis-free Sub-60-mV/decade switching. IEEE Electron Device Lett. 37, 245–248 (2016).

    CAS  Google Scholar 

  129. Wang, T. Y. et al. Ultralow power wearable heterosynapse with photoelectric synergistic modulation. Adv. Sci. 7, 1903480 (2020).

    Google Scholar 

  130. Bessonov, A. A. et al. Layered memristive and memcapacitive switches for printable electronics. Nat. Mater. 14, 199–204 (2015).

    CAS  Google Scholar 

  131. Tian, H. et al. Extremely low operating current resistive memory based on exfoliated 2D perovskite single crystals for neuromorphic computing. ACS Nano 11, 12247–12256 (2017).

    CAS  Google Scholar 

  132. Tian, H. et al. Anisotropic black phosphorus synaptic device for neuromorphic applications. Adv. Mater. 28, 4991–4997 (2016).

    CAS  Google Scholar 

  133. Tian, H. et al. Emulating bilingual synaptic response using a junction-based artificial synaptic device. ACS Nano 11, 7156–7163 (2017).

    CAS  Google Scholar 

  134. Zhong, Y. et al. Selective UV‐gating organic memtransistors with modulable levels of synaptic plasticity. Adv. Electron. Mater. 6, 1900955 (2020).

    CAS  Google Scholar 

  135. Liu, Y. H., Zhu, L. Q., Feng, P., Shi, Y. & Wan, Q. Freestanding artificial synapses based on laterally proton-coupled transistors on chitosan membranes. Adv. Mater. 27, 5599–5604 (2015).

    CAS  Google Scholar 

  136. Yang, Y., He, Y., Nie, S., Shi, Y. & Wan, Q. Light stimulated IGZO-based electric-double-layer transistors for photoelectric neuromorphic devices. IEEE Electron Device Lett. 39, 897–900 (2018).

    CAS  Google Scholar 

  137. He, Y., Yang, Y., Nie, S., Liu, R. & Wan, Q. Electric-double-layer transistors for synaptic devices and neuromorphic systems. J. Mater. Chem. C. 6, 5336–5352 (2018).

    CAS  Google Scholar 

  138. Lanza, M. et al. Recommended methods to study resistive switching devices. Adv. Electron. Mater. 5, 1800143 (2019).

    Google Scholar 

  139. Kuzum, D., Yu, S. & Wong, H. P. Synaptic electronics: materials, devices and applications. Nanotechnology 24, 382001 (2013).

    Google Scholar 

Download references

Acknowledgements

This work was supported by the National Natural Science Foundation of China (61925402, 61851402 and 61734003), Science and Technology Commission of Shanghai Municipality (19JC1416600), National Key Research and Development Program (2017YFB0405600), Shanghai Education Development Foundation and Shanghai Municipal Education Commission Shuguang Program (18SG01).

Author information

Author notes

  1. These authors contributed equally: Chunsen Liu, Huawei Chen, Shuiyuan Wang and Qi Liu.

Authors and Affiliations

  1. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China

    Chunsen Liu, Huawei Chen, Shuiyuan Wang, David Wei Zhang & Peng Zhou

  2. School of Computer Science, Fudan University, Shanghai, China

    Chunsen Liu & Yu-Gang Jiang

  3. Frontier Institute of Chip and System, Fudan University, Shanghai, China

    Qi Liu & Ming Liu

  4. Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

    Qi Liu & Ming Liu

Authors
  1. Chunsen Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Huawei Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Shuiyuan Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Qi Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Yu-Gang Jiang
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. David Wei Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Ming Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  8. Peng Zhou
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Peng Zhou.

Ethics declarations

Competing interests

The authors declare no competing interests.

Additional information

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Liu, C., Chen, H., Wang, S. et al. Two-dimensional materials for next-generation computing technologies. Nat. Nanotechnol. 15, 545–557 (2020). https://doi.org/10.1038/s41565-020-0724-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1038/s41565-020-0724-3

This article is cited by

Search

Advanced search

Quick links

Nature Briefing

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing