Skip to main content
SpringerLink
Log in

An Accurate Model for Threshold Voltage Analysis of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

In this article, an accurate representation of threshold voltage for double metal double gate (DMDG) device structure has been initiated. It is the lowest gate-source electromotive force at which the device can kick off to conduct. This paper also deliberates a comparison between the high-k medium and SiO2 as an oxide substance along with that considers the gate stack concept. Use of a promising high-k substance HfO2, reduces the small channel effect which is generated due to downsizing the device. The main challenge is to overcome the short channel effect that is generated due to scaling down the device. The model has been established by varying several criteria like channel length, film thickness, oxide thickness, temperature change, work function difference and drain source voltage. So that a clear reflection can be seen how the threshold voltage changes with several parameters. For all the cases, the implementations with high-k material show better execution in case of reducing short channel effects (SCEs) that are mainly generated due to reducing the device structure. In this article, the drain induced barrier lowering (DIBL) and subthreshold swing (SS) have also been modelled for the device structure. Extreme conformity can be noticed between the analytical model and TCAD result.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Nicollian, E. H. and Brews, J. R. (2002). MOS (metal oxide semiconductor) physics and technology. Wiley

  2. Neamen, D. (2017). Semiconductor physics and devices. McGraw Hill

  3. Cerdeira A, Moldovan O, Iñiguez B, Estrada M (2008) Modeling of potentials and threshold voltage for symmetric doped double gate MOSFETs. Solid State Electron 52:830–837

    Article  CAS  Google Scholar 

  4. Maity NP, Maity R, Thapa RK, Baishya S (2015) Effect of image force on tunneling current for ultra thin oxide layer based metal oxide semiconductor devices. Nanosci Nanotechnol Lett 7(4):331–333

    Article  Google Scholar 

  5. Maity NP, Maity R, Baishya S (2017) Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO2 based MOS devices. Supperlattices and Microstructures 111:628–641

    Article  CAS  Google Scholar 

  6. Cerdeira A, Iñiguez B, Estrada M (2008) Compact model for short channel symmetric doped double-gate MOSFETs. Solid State Electron 52:1064–1070

    Article  CAS  Google Scholar 

  7. Chiang TK (2016) A short channel effect degraded noise margin model for junctionless double gate MOSFET working on subthreshold CMOS logic gates. IEEE Trans. Electron. Devices 63(8):3354–3359

    Article  CAS  Google Scholar 

  8. Francis P, Terao A, Flandre D, Wiele F (1994) Modeling of ultrathin double-gate nMOS/SOI transistors. IEEE Transactions on Electron Devices 41(5):715–720

    Article  Google Scholar 

  9. Jin X, Liu X, Lee JH (2010) A continuous current model of fully-depleted symmetric double-gate MOSFETs considering a wide range of body doping concentrations. Semicond. Sci. Technol 25(5):055018

    Google Scholar 

  10. Chen S, Kuo JB (1996) Deep submicrometer double-gate fully depleted SOI PMOS devices: a concise Short-Channel effect threshold voltage model using a quasi-2D approach. IEEE Trans. on Electron Devices 43(9):1387–1393

    Article  CAS  Google Scholar 

  11. Kumar MJ, Chaudhury A (2004) Two-dimensional analytical modelling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans. on Electron. Devices 51(4):569–574

    Article  CAS  Google Scholar 

  12. Kumar MJ, Reddy GV (2004) Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs-A two dimensional analytical approach. Microelectron Eng 75:367–374

    Article  CAS  Google Scholar 

  13. Chaudhury A, Kumar MJ (2004) Investigation of the novel attributes of a fully depleted dual material gate SOI MOSFET. IEEE Trans on Electron Devices 51(9):1463–1467

    Article  Google Scholar 

  14. Saxena M, Halder S, Gupta M, Gupta RS (2002) Physics based analytical modelling of potential and electric field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency. IEEE Trans. on Electron. Devices 49(11):1928–1938

    Article  CAS  Google Scholar 

  15. Moldovan O, Cerdeira A, Jiménez D, Raskin JP, Kilchystka V, Flandre D, Collaert N, Iñiguez B (2007) Compact model for highly-doped double-gate SOI MOSFETs targeting basebad analog applications. Solid State Electron 51:655–661

    Article  CAS  Google Scholar 

  16. Saxena M, Haldar S, Gupta M, Gupta RS (2004) Design consideration for novel device architecture: hetero-material double gate (HEM-DG) MOSFET with sub-100nm gate length. Solid State Electronics 48:1169–1174

    Article  CAS  Google Scholar 

  17. Lin HH, Taur Y (2017) Effect of source drain doping on subthreshold characteristics of short channel DG MOSFETs. IEEE Trans Electron Devices 64(12):4856–4860

    Article  CAS  Google Scholar 

  18. Reddy GV, Kumar MJ (2005) A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation. IEEE Trans. on Nanotechnol 4(2):260–268

    Article  Google Scholar 

  19. Chakrabarti H, Maity R, Maity NP (2019) Analysis of surface potential for dual-material-double-gate MOSFET based on modelling and simulation. Microsyst Technol 25:4675–4684

    Article  CAS  Google Scholar 

  20. Chiang TK (2016) A quasi-two dimensional threshold voltage model for short channel junctionless double gate MOSFETs. IEEE Trans. Electron. Devices 59(9):2284–2289

    Article  Google Scholar 

  21. Chen Q, Harrell EM, Meindl JD (2003) A physical Short-Channel threshold voltage model for Undoped symmetric double-gate MOSFETs. IEEE Trans on Electron Devices 50(7):1631–1637

    Article  CAS  Google Scholar 

  22. Tsormpatzoglou A, Dimitriadis CA, Clerc R, Pananakakis G, Ghibaudo G (2008) Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs. IEEE Trans. Electron. Devices 55(9):2512–2516

    Article  Google Scholar 

  23. Goel E, Kumar S, Singh K, Singh B, Kumar M (2016) 2-D analytical Modelling of threshold voltage for Graded-Channel dual-material double-gate MOSFETs. IEEE Trans. Electron. Devices 63(3):966–973

    Article  CAS  Google Scholar 

  24. Darwin S, Samuel TSA (2019) A holistic approach on Junctionless dual material double gate (DMDG) MOSFET with high k gate stack for low power digital applications. Silicon 12:393–403

    Article  Google Scholar 

  25. Suzuki K (1995) Analytical models for n+-p+ double gate SOI MOSFET’s. IEEE Trans. on Electron. Devices 42(11):1940–1947

    Article  CAS  Google Scholar 

  26. Lee CW, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP (2010) Performance estimation of junctionless multigate transistors. Solid State Electron 54:97–103

    Article  Google Scholar 

  27. Tosaka Y, Suzuki K (1994) Scaling parameter dependent model for subthreshold swing S in double gate SOI MOSFET. IEEE Electron Device Letters 15(11):466–468

    Article  Google Scholar 

  28. Hamid HA, Guitart JR, Iniguez B (2007) Two dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs. IEEE Trans. Electron. Devices 54(6):1402–1408

    Article  Google Scholar 

  29. Maity NP, Maity R, Baishya S (2018) A tunneling current model with a realistic barrier for ultra thin high-k dielectric ZrO2 material based MOS devices. Silicon 10:1645–1652

    Article  CAS  Google Scholar 

  30. Maity NP, Maity R, Maity S, Baishya S (2019) Comparative analysis of the quantum FinFET and Trigate FinFET based on modeling and simulation. J Comput Electron 18(2):492–499

    Article  CAS  Google Scholar 

  31. Maity NP, Maity R, Baishya S (2019) An analytical model for the surface potential and threshold voltage of a double gate Heterojunction tunnel FinFET. J Comput Electron 18(1):65–75

    Article  CAS  Google Scholar 

  32. Maity, N. P., Maity, R., Dutta, S., Deb, S., Saravani, K.G., Rao, K. S., and Baishya, S. (2020). Effects of hafnium oxide on surface potential and drain current models for subthreshold Short Channel metal-oxide-Semoconductor-field-effect-transistor. Transactions on electrical and electronic materials. Online published on 23rd Feb., 2020, DOI: https://doi.org/10.1007/s42341-020-00181-4

  33. Jelodar MS, Ilatikhameneh H, Kim S, Ng K, Klimeck G (2016) Optimum high-k oxide for the best performance of ultrascaled double-gate MOSFETs. IEEE Trans on Nanotechnol 15:904–910

    Article  Google Scholar 

  34. Narang R, Saxena M, Gupta RS, Gupta M (2013) Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans Nanotechnol 12(6):951–957

    Article  CAS  Google Scholar 

  35. Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep submicron SOI MOSFETs for improved reliability: a review. IEEE Trans on Device and Materials Reliability 4:99–109

    Article  Google Scholar 

  36. Maity, N. P., Maity, R., Maity S, and, Baishya, S. (2019). A new surface potential and drain current model of dual material gate Short Channel metal oxide semiconductor field effect transistor in sub-threshold regime: application to high-k material HfO2. J of Nanoelectronics & Optoelectronics, Vol. 14, pp. 868–876

  37. Maity NP, Maity R, Thapa RK, Baishya S (2016) A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices. Superlattice Microst 95:24–32

    Article  CAS  Google Scholar 

  38. Maity NP, Pandeya A, Chakraborty S, Roy M (2012) High-K HfO2 Based Metal-Oxide-Semiconductor Devices using Silicon and Silicon Carbide Semiconductor. J Nano-Electron Phys 4(10):948–956

  39. Maity NP, Thakur RR, Maity R, Thapa RK, Baishya S (2015) Interface Charge Density Measurement for Ultra Thin ZrO2 Material Based MOS Devices Using Conductance Method. Procedia Computer Science 57:761–765.

  40. Panda A, Ranjan Das S, Dhupal D (2019) Machinability investigation of HSLA steel in hard turning with coated ceramic tool: assessment, Modelling, optimization and economic aspects. J Adv Manuf Syst 18(04):625–655

    Article  Google Scholar 

  41. Behera, R. K., and Das, S. R. (2019). Modelling and optimization of technological parameters in hot abrasive jet machining of alumina ceramic. Matériaux & Techniques, vol. 107, no. 6, pp. 603

  42. Dixit SR, Das SR, Dhupal D (2019) Parametric optimization of Nd:YAG laser microgrooving on aluminum oxide using integrated RSM-ANN-GA approach. Journal of Industrial Engineering International 15(2):333–349

    Article  Google Scholar 

  43. Panda, A., Das, S. R., and Dhupal, D. (2018). Experimental investigation, modelling and optimization in hard turning of high strength low alloy steel (AISI 4340). Matériaux & Techniques, vol. 106, no. 4, pp. 404

  44. Dubey S, Tiwari P, Jit S (2011) A two-dimensional model for the subthreshold swing of short-channel double-gate metal–oxide–semiconductor field effect transistors with a vertical Gaussian-like doping profile. Journal of applied Physics 109(5):054508 1–054508 7

    Article  Google Scholar 

  45. Zou X, Fang G, Wan J, He X, Wang H, Liu N, Long H, Zhao X (2011) Improved Sibthresold swing and gate Bias stressing stability of p-type Cu2O thin film transistors using a HfO2 high-k gate dielectric grown on a SiO2/Si substrate by pulsed laser ablation. IEEE Trans. on Electron Devices 58(7):2003–2007

    Article  CAS  Google Scholar 

Download references

Acknowledgements

The Authors are highly indebted to National Institute of Technology, Silchar, and Mizoram University (A Central University) for supporting this technical work.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Mizoram University (A Central University), Aizawl, 796 004, India

    Himeli Chakrabarti, Reshmi Maity & N. P. Maity

  2. Department of Electronics and Communication Engineering, Regent Education and Research Foundation Group of Institutions, Kolkata, 700 121, India

    Himeli Chakrabarti

  3. Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, 788 010, India

    S. Baishya

Authors
  1. Himeli Chakrabarti
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Reshmi Maity
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. S. Baishya
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. N. P. Maity
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to N. P. Maity.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Chakrabarti, H., Maity, R., Baishya, S. et al. An Accurate Model for Threshold Voltage Analysis of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor. Silicon 13, 1851–1861 (2021). https://doi.org/10.1007/s12633-020-00553-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-020-00553-8

Keywords

Search

Navigation