Abstract
Decreasing the scale of transistors and their voltages and exponential increase in the transistor counts have made the nowadays digital integrated circuits more susceptible to transient hardware errors (soft errors). One of the interesting features of software systems is that a considerable number of soft errors are inherently masked at software level. The likelihood of error masking (error deration) in the software may be influenced by the Algorithm, data structures and programming paradigms used in the software. One of the main research questions in this field of study is that how can software reliability be improved against soft errors without external redundancy and only by selecting appropriate software structures. This paper investigates the inherent effects of the underlying data structures on the rate of error deration and program reliability. To attain this goal, five different benchmark programs were implemented by four different data structures, i.e. Array, Binary-search Tree, One-way linked list and Two-way linked list; profiling experiments were performed on the benchmarks to identify those features of the data structures which affect the rate of error-deration. Then, in order to quantify and examine the inherent reliability of the data structures, about 5,600,000 faults were injected into the benchmark programs. The results show that about 53.95% of faults in the Array based programs are masked; this figure for Binary-search tree, One-way linked list and Two-way linked list are 40.16%, 44.02% and 42.73%, respectively. We found that Array and BST as two different data structures have the highest and lowest inherent reliability respectively. These findings enable the software developers to select the most reliable data structures for developing reliable programs without external redundancy.
Similar content being viewed by others
Notes
The terms “error masking” and “error deration” are equivalent and are used interchangeably with the same meaning in this paper.
The terms “software” and “program” are used interchangeably with the same meaning in this paper.
References
Aghdam ZK, Arasteh B (2017) An efficient method to generate test data for software structural testing using artificial bee colony optimization algorithm. Int J Softw Eng Knowl Eng 27(6):951–966
Aidemark J, Folkesson P, Karlsson J (2001) Path-based error coverage prediction. In: Proceedings seventh international on-line testing workshop, Taormina, pp 14–20. https://doi.org/10.1109/olt.2001.937811
Ammann P, Offutt J (2016) Introduction to software testing. Cambridge University Press. ISBN: 9781107172012
Arasteh B, Najafi A (2018) Programming guidelines for improving software resiliency against soft-errors without performance overhead. J Comput 100:971–1003
Arasteh B, Miremadi SG, Am Rahmani (2014) Developing inherently resilient software against soft-errors based on algorithm level inherent features. J Electron Test 30(2):193–212
Arasteh B, Bouyer A, Pirahesh S (2015) An efficient vulnerability-driven method for hardening a program against soft-error using genetic algorithm. Comput Electr Eng 48:25–43
Austin T, Larson E, Ernst D (2002) SimpleScalar: an infrastructure for computer system modeling. IEEE Comput 35(2):59–67
Barbosa R, Vinter J, Folkesson JP, Karlsson J (2005) Assembly-level pre-injection analysis for improving fault injection efficiency. In Proceedings seventh international dependable computing, lecture notes in computer science, vol 3463, Springer, Berlin
Benso A, Di Carlo S, Di Natale D, Prinetto P, Tagliaferri L (2003) Data criticality estimation in software application. In: International test conference, pp 802–810
Borodin D, Juurlink BHH (2010) Protective redundancy overhead reduction using instruction vulnerability factor. In: ACM international conference on computing frontiers, Italy, pp 319–326
Butts JA, Sohi G (2002) Dynamic dead-instruction detection and elimination. In: 10th International conference on architectural support for programming languages and operating systems (ASPLOS X), pp 199–210
Cook JJ, Zilles C (2008) A characterization of instruction-level error derating and its implications for error detection. In: IEEE international conference on dependable systems and networks (DSN)
Dixit A, Wood A (2011) The impact of new technology on soft error rates. In: Proceedings of the IEEE workshop on silicon errors in logic system
Evers M (2000) Improving brnach prediction by understanding branch behaviour. PhD. thesis, University of Michgan
Fazeli M, Farivar R, Miremadi SG (2005) A software-based concurrent error detection technique for PowerPC processor-based embedded systems. In: 20th IEEE international symposium on defect and fault tolerance in VLSI systems, pp 266–274
Folkesson P, Karlsson J (1999) Considering workload input variations in error coverage estimation. In: Proceedings of the third European dependable computing conference on dependable computing (EDCC-3), pp 171–190
Hiller M, Jhumka A, Suri N (2001) An approach for analyzing the propagation of data errors in software. In: IEEE international conference on dependable systems and networks (DSN)
Jantz MJ, Kulkarni PA (2012) Understand and categorize dynamically dead instructions for contemporary architectures. In: International conference on interaction between compilers and computer architectures (INTERACT), pp 25–32
Jiesheng W, Rashid L, Pattabiraman K, Gopalakrishnan S (2011) Comparing the effects of intermittent and transient hardware faults on programs. In: International conference on dependable systems and networks (DSN), pp 53–58
Karnik T, Hazucha P, Patel J (2004) Characterization of soft errors caused by single event upsets in CMOS process. IEEE Trans Depend Secure Comput 1(2):128–143
Kleinberg J, Tardos E (2004) Algorithm design. Addison-Wesley. ISBN: 0-321-29535-8
Li X (2009) Exploiting inherent program redundancy for fault tolerance. PHD thesis in University of Maryland
Lu JS, Li F, Degalahal V, Kandemir M, Vijaykrishnan N, Irwin MJ (2005) Compiler-directed instruction duplication for soft error detection. In: Design, automation and test in Europe conference, pp 1056–1057
Messer A (2004) Susceptibility of commodity systems and software to memory soft errors. IEEE Trans Comput 53(12):1557–1568
Mukherjee SS, Weaver C, Emer J, Reinhardt SK, Austin T (2003) A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In: 36th Annual IEEE/ACM international symposium on micro architecture, pp 29–40
Nair A, John LK, Eeckhout L (2010) AVF stressmark: towards an automated methodology for bounding the worst-case vulnerability to soft errors. In: 43rd annual IEEE/ACM international symposium on microarchitecture (MICRO), pp 125–136
Norusis M (2008) SPSS 16.0 guide to data analysis. Prentice Hall. ISBN: 0-136-06136-2
Oh N, Mccluskey EJ (2002) Error detection by selective procedure call duplication for low energy consumption. IEEE Trans Reliab 51(4):392–402
Oh N, Shirvani PP, McCluskey EJ (2002) Error detection by duplicated instructions in super-scalar processors. IEEE Trans Reliab 51(1):63–75
Rebaudengo M, Sonza Reorda M, Torchiano M, Violante M (1999) Soft-error detection through software fault-tolerance techniques. In: IEEE international symposium on defect and fault tolerance in VLSI systems, pp 210–218
Rebaudengo M, Sonza Reorda M, Torchiano M, Iolante M (2001) A source-to-source compiler for generating dependable software. In: IEEE international workshop on source code analysis and manipulation, pp 33––42
Roberts MJ, Russo R (1999) A student’s guide to analysis of variance. Routledge Publication. ISBN:0-415-16564-2
Saggese GP, Vetteth A, Kalbarczyk Z, Iyer R (2005) Microprocessor sensitivity to failures: control versus execution and combinational versus sequential logic. In: International conference on dependable systems and networks (DSN), pp 760–769
Saggese GP, Wang NJ, Kalbarczyk ZT, Patel SJ, Iyer RK (2005b) An experimental study of soft errors in microprocessors. IEEE Micro 25(6):30–39
Sahoo SK (2008) Using likely program invariants to detect hardware errors. In: IEEE international conference on dependable systems and networks (DSN)
Sangchoolei B, Ayatolahi F, Barbosa R, Karlson J (2013) Benchmarking the hardware error sensitivity of machine instructions. In: IEEE workshop on slicon errors in logic: system effects (SELSE)
Savino A, Carlo SD, Politano G, Benso A, Dnatale G (2012) Statistical reliability estimation of microprocessor-based systems. IEEE Trans Comput 61(11):1521–1534
Shivakumar P, Kistler M, Keckler S, Burger D, Alvisi L (2002) Modeling the effect of technology trends on soft error rate of combinational logic. In: International conference on dependable systems and networks (DSN)
Shuguang F, Shantanu G, Ansari A, Mahlke S (2010) Shoestring: probabilistic soft-error resilience on the cheap. In: 15th international conference on architectural support for programming languages and operating systems
Skarin D, Karlson J (2008) Software implementd detection and recovery of soft errors in a brake-by-wire system. In: IEEE international european dependable computing conference (EDCC)
Slegel TJ, Averill RM, Check MA, Giamei BC, Krumm BW, Krygowski CA, Li WH, Liptay JS, MacDougall JD, McPherson TJ, Navarro JA, Schwarz EM, Shum K, Webb CF (1999) IBM’s S/390 G5 microprocessor design. IEEE Micro 19(2):12–23
Sridharan V, Kaeli DR (2010) Using PVF traces to accelerate AVF modeling. In: Proceedings of the IEEE workshop on silicon errors in logic: system effects, Stanford, California
Thaker D, Franklin D, Oliver J, Biswas S, Lockhart D, Metodi T, Chong FT (2006) Characterization of error-tolerant applications when protecting control data. In: IEEE international symposium on workload characterization
Thomas H (2001) Introduction to algorithms. The MIT Press. ISBN: 0-262-03293-7
Wang F, Agrawal VD (2009) Soft error rates with inertial and logical masking. In: 22nd international conference on VLSI design
Wang N, Fertig M, Patel S (2003) Y-branches: when you come to a fork in the road, take it. In: International conference on parallel architectures and compilation techniques
Xiong L, Tan Q, Xu J (2011) Soft error mask analysis on program level. In: 10th International conference on network
Xu X, Li M (2012) Understanding soft error propagation using efficient vulnerability-driven fault injection. In: IEEE international conference on dependable systems and networks (DSN)
Zhang M, Shanbhag N (2004) A soft error rate analysis methodology. In: IEEE/acm international conference on computer-aided design
Zhang B, Wang WS, Orshansky M (2006) FASER: fast analysis of soft error susceptibility for cell-based designs. In: 7th International symposium on quality electronic design
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Arasteh, B., Khosroshahizadeh, S. Software reliability enhancement against hardware transient errors using inherently reliable data structures. Int J Syst Assur Eng Manag 11, 883–898 (2020). https://doi.org/10.1007/s13198-020-01011-9
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s13198-020-01011-9