Abstract
In this letter, a capacitor-splitting switching algorithm for successive approximation register (SAR) analog-to-digital converters is proposed. To achieve low power, the hybrid switching scheme is involved. The monotonic switching technique is used during the last bit cycle; for other bit cycles except the first one, the switching is based on MSB and the former determined bit. Besides, the common-mode voltage remains constant during the entire bit cycles except the last one. In addition, the proposed capacitor-splitting switching process is easily performed, relaxing the design complexity of the SAR control logic. As a result, the proposed switching scheme is a better trade-off among energy-efficiency, common-mode voltage variation, and logic complexity.
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Acknowledgements
This work was supported by the Scientific Research Foundation of Fujian University of Technology (GY-Z14072, GY-Z18182), and the Fujian Provincial Education Fund (JAT170372, JT180352).
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Wang, H., Chen, Z., Xie, W. et al. A capacitor-splitting DAC switching scheme with high power-efficiency and low common-mode voltage variation. Analog Integr Circ Sig Process 104, 343–349 (2020). https://doi.org/10.1007/s10470-020-01677-y
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DOI: https://doi.org/10.1007/s10470-020-01677-y