Single event transient hardened delay cell for a differential ring VCO

Highlights

• It reports a new SET hardened complementary delay cell topology (SET-H CDC) for radiation hardness of differential ring (DR-VCO) designed using a 90 nm CMOS process running at 2.6 GHz frequency.

• The phase displacement caused by SET ion hit for the proposed SET-H CDC delay cell is compared with the wide tuning delay cell and complementary delay cell (CDC). A theoretical analysis for choosing optimal resistor value for SET-H CDC delay cell is discussed.

• The SET-H CDC delay cell topology achieves a 17% improvement in rms ISF compared to the wide tuning delay cell and 1.2% improvement compared to the CDC delay cell.

Abstract

This paper presents a new single event transient hardened complementary delay cell (SET-H CDC) for radiation environment. The performance of the proposed topology has been compared with the existing radiation-hardened delay cell topologies called wide tuning delay cell and complementary delay cell (CDC). A three-stage VCO has been designed with each of the delay cell topologies for low power consumption while maintaining maximum swing. The VCO is designed using 90 nm CMOS process technology work with 1 Volt DC supply operating at 2.6 GHz frequency. The proposed topology shows better single event tolerance and reduced Impulse Sensitivity Function (ISF) while maintaining a rail-rail swing over a wide frequency tuning range. The proposed topology achieves a 17% improvement in rms ISF compared to wide tuning delay cell and 1.2% improvement compared to CDC delay cell.

Introduction

THE single-event transient (SET) vulnerability of digital, analog, and mixed-signal circuits used in harsh environments such as space and the nuclear application has been a major reliability concern in recent days [[1], [2], [3], [4]]. The vulnerability of SET increases with the decreasing feature size and increasing frequency, especially in the microelectronic circuits designed using CMOS process technology below 100 nm [5]. The mixed-signal circuits such as Phase Locked Loop (PLL) and Delay Locked Loops (DLL) are commonly used for clock distribution, clock recovery, and frequency synthesis applications such as Local Oscillator (LO) clock generation in transceiver blocks. Any SET hit in a VCO placed in a synthesizer block could produce adjacent channel frequency leading to interference in the receiver channel [6].To reduce the SET vulnerability of PLL a series resistor was used to isolate the low pass filter voltage from the charge pump of the PLL [7,8]. A similar approach has been used for the SRAM circuit to decouple the output nodes for improved radiation tolerance [9].

Since the VCO [10] is a dominant single event susceptible block of PLL, several works have been reported on radiation hardening and mitigation techniques for VCOs [[10], [11], [12], [13], [14], [15], [16]]. Ring oscillators are popular as it consumes less power, area, and simplicity in architecture. In the current starved single-ended structure, the maximum phase displacement due to SET can be reduced by increasing the number of delay cell stages [10]. However, Ring oscillator PLL shows severe degradation performance compared to the LC-based PLL for higher Total Ionizing Dose (TID) test [11]. Radiation tolerant PLL VCO with optimized voltage controlled oscillator (VCO) is proposed in [12] as it phase noise performance of LC-tank VCO is superior compared to ring oscillator VCOs but at the cost of more area and power [13]. Similar works on SET induced frequency response and RHBD technique for LC tank VCOs have been studied in [15,16]. An improved complementary differential pair topology was proposed for hardening the voltage-controlled delay line (VCDL) in [17]. To further harden the VCDL, an error correction circuit designed using a combinational circuit was utilized to reduce the missing pulses [18]. Experimental determination of phase-dependent sensitivity of the single event effects (SEEs) of high-speed PLL circuit was presented in [19] using periodic laser injection.

In [20], it was shown that increasing the number of stages in DR-VCO reduces the phase perturbation and erroneous cycles caused by ion hit in standalone VCO and as part of a PLL. However, increasing the delay stages increases power consumption and area. To address this issue, in [21] the suitability of different conventional delay cell topologies such as diode-connected load, triode load, Maneatis delay cell, and wide tuning topologies [22,23] were studied in a 3-stage DR-VCO. It was shown that the wide tuning topology has better SET tolerance compared to the other conventional differential delay cell structures.

In this paper, a new differential delay cell topology is proposed that has a built-in resilience against SET while consuming less power. The phase displacement sensitivity of the proposed delay cell is examined in terms of ISF (Impulse sensitivity function). The phase error induced by a SET hit in the 3-stage DR-VCO running at 2.6 GHz designed using proposed delay cell is compared with the existing wide tuning topologies. The simulation result shows that the proposed topology achieves reduced phase displacement following the SET hit in the VCO.

This paper is organized into five sections. Section 2 presents a brief review of ISF and its use in mitigating the SET. Section 3 describes the existing radiation-hardened topologies considered in this work and proposed topology operation. Section 4 presents the SET impact on the VCO delay cell topologies. The conclusion comprises Section 5.