Elsevier

Solid-State Electronics

Volume 171, September 2020, 107866
Solid-State Electronics

Modeling source/drain lateral Gaussian doping profile of DG-MOSFET using Green’s function approach

https://doi.org/10.1016/j.sse.2020.107866Get rights and content

Abstract

Present work has used Green’s function approach to derive a two-dimensional analytical model of the double gate (DG) MOSFET at the subthreshold regime of operation that considers the effect of inevitable source/drain (S/D) lateral Gaussian doping profile. The non-integrable Gaussian term has been converted into an integrable function for accurate Fourier coefficient calculation which is then used to determine the potential equations of all three regions. These equations are then utilized to formulate channel current (Isub), the threshold voltage (Vt) roll off and subthreshold slope (SS) of the device. The effects of lateral Gaussian profile at different gate length (L), and for devices with different combinations of oxide thickness (tox) and channel thickness (tsi) have been investigated. The results show that the S/D Gaussian doping profile has severe effects at scaled gate lengths, where gate electrostatic control is of paramount importance.

Introduction

The doping level of source/drain regions is held higher during device fabrication step to regulate the device parasitics so that the performance is not hampered [1]. The loss of gate electrostatic integrity becomes more prominent as the scaling limits of MOSFETs enter into the nanometer regime, thereby aggravating the short channel effects (SCE) [2], [3]. International Technology Roadmap for Semiconductor (ITRS) [4] suggests the creation of ultra-shallow junction (USJ) to restrict the lateral spread of source/drain (S/D) electric field in the channel region so that the gate electrostatic integrity is restored. The development of USJ is, however, regulated through defect formation, junction leakage, effective process and temperature control, equipment maturity, effectiveness in cost, etc. Molecular monolayer doping (MLD) and microwave annealing are the recent advanced improved technique, promising the ultra-shallow junction (USJ) formation up to ~12 nm [5], [6], [7]. Although Ang et al. [5], reports ~5 nm junction depth, however it is limited to spreading of doping profile from 1022 cm−3 to 5 × 1018 cm−3 [5]. For multigate device, higher channel doping is hardly preferred to avoid random doping fluctuation issue. Therefore, we consider ~12 nm of USJ, when the S/D region is doped with 1020 cm−3 and the channel region is doped intrinsically with acceptor concentration (Na) of 1016 cm−3 [5], [6], [7], [8], [9]. Modeling of the multigate device must include this kind of lateral spread of S/D doping profile which is inevitable in practical device when it is scaled into nanometer regime.

The Gaussian function has non-integrable nature over a finite interval. Therefore, to obtain an analytical solution of the Poisson equation, for the first time, Dasgupta et al. [10] have converted the Gaussian function into a new function which is integrable. Initially, many research groups have suggested the use of various methods to model the vertical Gaussian doped DG-MOSFET [11], [12], [13], [14], [15]. In [11], [12] the analytical model of vertical Gaussian doped DG-MOSFET and FD-SOI MOSFET have been proposed using Polynomial approach, while in [13], [14], [15] model for DG-MOSFET and JLDG-MOSFET are proposed using Evanescent-mode analysis (EMA). However, for the first time, Nandi et al. [16] have suggested analytical model of DG-MOSFET with S/D lateral Gaussian doping profile, using Polynomial approach that involves approximation of Gaussian term by its absolute value at each point of the channel because integrating the Gaussian terms involved using trivial mathematical techniques is difficult. Second, the approach considers 1-D boundary conditions at the Si-SiO2 interface, hence the method is restricted to long channel device only. Similarly, in 2016, K. Singh et al. [17] also presented an analytical model of underlap DG-MOSFET with S/D lateral Gaussian doping profile using the polynomial approach and conformal mapping technique.

There are many available mathematical models, such as polynomial approach [11], [12], evanescent mode analysis [18], [13], [14], [15], empirical expressions, charge sharing approach, and Green’s function approach that can explain the operation of the device under the subthreshold regime. However, green’s function approach can accurately model the 2-D potential distribution of both oxide and channel region without any approximation [19], [20]. In 2017, Nandi et al. [21], [22], presented an accurate analytical model of DG-MOSFET as well as JLDG-MOSFET using Green’s function approach which can precisely estimate channel electrostatics for distinct doping level of both short and long channel and higher as well as lower tsi /tox ratio-based devices. Green’s function approach is a generic approach which can also be used to derive a mathematical model of complex structures. Recently Nandi et al. [23] have also extended the Green’s function method to develop an accurate analytical model of complex gate stack DG-MOSFET.

Present work has further extended the Green’s function approach to solve the 2-D Poisson equation, taking into account the impact of S/D Gaussian profile in the channel region forming USJ. This kind of modeling not only serves for characterization and benchmarking purpose but also provides a firm guideline for generating the compact model of nanoscale DG-MOSFET. Fig. 1 shows the nonzero lateral straggle perspective of DG-MOSFET, where USJ is created in the channel area near S/D ends. The Fourier coefficient of the Gaussian term (USJ region of the channel) has been calculated correctly in the present work. Subsequently, we have derived potential equations of all three regions (I, II, III). These derived equations are used to formulate subthreshold current (Isub), threshold voltage (Vt) roll-off and subthreshold slope (SS) of the device to show the effect of lateral electric field spread through S/D Gaussian profile on these parameters.

Section snippets

Proposed integrable function

The electrostatic potential distribution in the channel region of MOSFET is generally derived by solving Poisson’s equation2ψx2+2ψy2=qNa-εSi-qNSD+(x)εSi

The lateral S/D Gaussian profile (NSD+(x)) in the channel region is modeled as:NSD+(x)=NSD(p)e-x22σ2+NSD(p)e-L-x22σ21+sDeEF-ED/kTwhere (NSD(p)) is the peak of the Gaussian doping profile,SD is spin degeneracy factor and σ is the lateral straggle of S/D profile. The positions of Fermi level EF and donor level ED with respect to the valence

Model formulation

The degenerated S/D regions (0 to Seff and Deffto L) are treated as an extension of S/D ends from its original positions (0 and L). Subsequently, using Green’s function approach, the simplified form of the 2-D potential distribution of the channel region (from Seff to Deff) considering S/D lateral Gaussian profile, is derived as:ψIIx,y=2Leffn=1sinknx-Seffεsiknsinhkntsi×Dsfncoshkntox+tsi-y-Dsbncoshkntox-y+ψSeff+x-SeffVDS/Leff+qNSD+x-Na-x-SeffDeff-x/2εsi

where the Fourier coefficient Dsfnis

Conclusion

The present research discusses the viable use of Green's function approach to target a precise answer to the 2-D Poisson’s equation in DG-MOSFET, considering the effect of inevitable S/D Gaussian doping profile in the channel region. The potential equation is obtained with an accurate calculation of the Fourier coefficient governing the Gaussian term. The derived channel potential equation is further used to formulate the expressions for subthreshold current (Isub), Vt roll-off, and the

Declaration of Competing Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Alok Kumar Shukla is currently pursuing the M. Tech. degree with School of VLSI Design and Embedded System, National Institute of Technology Kurukshetra, Kurukshetra, India. His current research interests include device modeling of multigate semiconductor devices, and analog/digital circuit design.

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    Alok Kumar Shukla is currently pursuing the M. Tech. degree with School of VLSI Design and Embedded System, National Institute of Technology Kurukshetra, Kurukshetra, India. His current research interests include device modeling of multigate semiconductor devices, and analog/digital circuit design.

    Ashutosh Nandi received his Ph.D. degree from IIT Roorkee, India in 2015. He is currently an Assistant Professor with Department of Electronics and Communication Engineering, NIT Kurukshetra, India. His research interests include low power VLSI design, device circuit co-design in digital/analog domain and device modeling of multigate semiconductor devices.

    S. Dasgupta received Ph.D. degree from IIT, BHU, India in 2000. He is currently a Professor with Department of Electronics and Communication Engineering, IIT Roorkee, India. His research interests include ultra low power applications, radiation effects on ICs, semiconductor devices and device modeling.

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