Abstract
Graphene nanoribbons (GNRs) are a good replacement material for silicon to overcome short-channel effects in nanoscale devices. However, with continuous technology scaling, the variability of device parameters also increases. Indeed, process, voltage, and temperature (PVT) variations affect the performance of GNR devices because of their small size. Moreover, the bandgap of GNRs is strongly affected by the number of carbon atoms across the channel width. This paper accurately evaluates the impact of such PVT variations on the performance of circuits based on Schottky barrier (SB)-type GNR field-effect transistors (SB-GNRFETs) in terms of their timing parameters, power, and energy–delay product (EDP). Extensive simulations and stability analysis are performed on both flip-flop and conventional six-transistor static random-access memory (6T SRAM) cells made using SB-GNRFETs under these variations. A statistical analysis of the impact of the PVT variations on the SB-GNRFET-based flip-flop is also performed using Monte Carlo simulations, considering the variation of one or all of the parameters, with or without line-edge roughness effects.
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References
Plummer, J.D., Griffin, P.B.: Material and process limits in silicon VLSI technology. Proc. IEEE 89(3), 240–258 (2001). https://doi.org/10.1109/5.915373
Schwierz, F.: Two-dimensional electronics—prospects and challenges. J. Electron. (2016). https://doi.org/10.3390/electronics5020030
Novoselov, K.S., Fal, V., Colombo, L., Gellert, P., Schwab, M., Kim, K.: A roadmap for graphene. Nature 490(7419), 192–200 (2012). https://doi.org/10.1038/nature11458
Geim, A.K., Novoselov, K.S.: The rise of graphene. Nat. Mater. 6(3), 183–191 (2007). https://doi.org/10.1038/nmat1849
Castro Neto, A.H., Guinea, F., Peres, N.M.R., Novoselov, K.S., Geim, A.K.: The electronic properties of graphene. Rev. Mod. Phys. (2009). https://doi.org/10.1103/RevModPhys.81.109
Du, X., Skachko, I., Barker, A., Andrei, E.Y.: Approaching ballistic transport in suspended graphene. Nat. Nanotechnol. 3(8), 491–495 (2008). https://doi.org/10.1038/nnano.2008.199
Balandin, A.A., Ghosh, S., Bao, W., Calizo, I., Teweldebrhan, D., Miao, F., et al.: Superior thermal conductivity of single-layer graphene. Nano Lett. 8(3), 902–907 (2008). https://doi.org/10.1021/nl0731872
Park, S., Ruoff, R.S.: Chemical methods for the production of graphenes. Nat. Nanotechnol. 4(4), 217–224 (2009). https://doi.org/10.1038/nnano.2009.58
Banadaki, Y., Mohsin, K., Srivastava, A.: A graphene field effect transistor for high temperature sensing applications. Proc. (SPICE Smart Structure/NDE: Nano-, Bio-, and Info-Tech Sens Syst SSN06) (2014). https://doi.org/10.1117/12.2044611
Heer, De, Walt, A., Berger, C., Wu, X., First, P.N., Conard, E.H., Li, A., Li, T., Sprinkle, M., Hass, J., Sadowski, M.L., Potemski, M., Martinez, G.: Epitaxial graphene. Solid State Commun. (2007). https://doi.org/10.1016/j.ssc.2007.04.023
Gholipour, M., Chen, Y.-Y., Sangai, A., Masoumi, N., Chen, D.: Analytical SPICE-compatible model of Schottky-barrier-type GNRFETs with performance analysis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (2016). https://doi.org/10.1109/TVLSI.2015.2406734
Joshi, S., Albalawi, U.: Statistical process variation analysis of Schottky-barrier type GNRFET for RF application. Int. Conf. Current Trends Comput., Electr., Electron. Commun. (CTCEEC) (2017). https://doi.org/10.1109/CTCEEC.2017.8455156
Chen, Y.-Y., Sangai, A., Rogachev, A., Gholipour, M., Iannaccone, G., Fiori, G., et al.: A SPICE-compatible model of MOS-type graphene nano-ribbon field-effect transistors enabling gate-and circuit-level delay and power analysis under process variation. IEEE Trans. Nanotechnol. (2015). https://doi.org/10.1109/TNANO.2015.2469647
Gholipour, M., Chen, Y.-Y., Sangai, A., Chen, D.: Highly accurate SPICE-compatible modeling for single-and double-gate GNRFETs with studies on technology scaling. Proc. Conf. Design, Autom. Test Europe (2014). https://doi.org/10.7873/DATE.2014.133
Chen, Y.-Y., Rogachev, A., Sangai, A., Iannaccone, G., Fiori, G., Chen, D.: A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation. Design, Autom. Test Europe Conf. Exhib. (DATE) (2013). https://doi.org/10.7873/DATE.2013.359
Anil, D.G., Bai, Y., Choi, Y.: Performance evaluation of ternary computation in SRAM design using graphene nanoribbon field effect transistors. IEEE 8th Ann. Comput. Commun. Workshop Conf. (CCWC) (2018). https://doi.org/10.1109/CCWC.2018.8301723
Aradhya, H.R., Madan, H., Megaraj, T., Suraj, M., Karthik, R., Muniraj, R.: GNRFET based 8-bit ALU. Int. J. Electron. Commun. Eng. (IJECE) 5(1), 45–54 (2016)
Joshi, S., Mohanty, S.P., Kougianos, E., Yanambaka, V.P.: Graphene nanoribbon field effect transistor based ultra-low energy SRAM design. IEEE Int. Symp. Nanoelectron. Inform. Syst. (iNIS) (2016). https://doi.org/10.1109/iNIS.2016.028
Singh, P., Chandel, R., Sharma, N.: Stability analysis of SRAM cell using CNT and GNR field effect transistors. Int. Conf. Contemp. Comput. (IC3) (2017). https://doi.org/10.1109/IC3.2017.8284335
Forzan, C., Pandini, D.: Statistical static timing analysis: a survey. Integration 42(3), 409–435 (2009). https://doi.org/10.1016/j.vlsi.2008.10.002
Mittal, S.: A survey of architectural techniques for managing process variation. ACM Comput. Surv. (CSUR) 48(4), 54 (2016). https://doi.org/10.1145/2871167
Liu, J.J.-H., Zeng, J.-K., Hong, A.-S., Chen, L., Chen, C.C.P.: Process-variation statistical modeling for VLSI timing analysis. Int. Symp. Qual. Electron. Design. (isqed 2008) (2008). https://doi.org/10.1109/ISQED.2008.4479828
Sapatnekar, S.S.: Overcoming variations in nanometer-scale technologies. IEEE J. Emerg. Sel. Top. Circuits Syst. 1(1), 5–18 (2011). https://doi.org/10.1109/JETCAS.2011.2138250
Pandit, S., Mandal, C., Patra, A.: Nano-scale CMOS analog circuits: models and CAD techniques for high-level design, 1st edn. CRC Press, London (2014). https://doi.org/10.1201/9781315216102
Cheng, L.: Statistical analysis and optimization for timing and power of VLSI circuits. University of California, Los Angeles (2010)
Bhunia, S., Mukhopadhyay, S.: Low-power variation-tolerant design in nanometer silicon. Springer Science & Business Media, Berlin (2010). https://doi.org/10.1007/978-1-4419-7418-1
Mohsin, A.: Graphene synthesis and characterization on copper. https://doi.org/10.17077/etd.xkpszqo8 (2012)
Chilstedt, S., Dong, C., Chen, D.: Carbon nanomaterial transistors and circuits. In: Transistors: types, materials and applications, pp. 1–34. Nova Sience Pub., New York (2010)
Son, Y.-W., Cohen, M.L., Louie, S.G.: Energy gaps in graphene nanoribbons. Phys. Rev. Lett. 97(21), 216803 (2006). https://doi.org/10.1103/PhysRevLett.97.216803
Singh, V., Joung, D., Zhai, L., Das, S., Khondaker, S.I., Seal, S.: Graphene based materials: past, present and future. Prog. Mater Sci. 56(8), 1178–1271 (2011). https://doi.org/10.1016/j.pmatsci.2011.03.003
Marmolejo-Tejada, J.M., Velasco-Medina, J.: Review on graphene nanoribbon devices for logic applications. Microelectron. J. 48, 18–38 (2016). https://doi.org/10.1016/j.mejo.2015.11.006
Chen, Y.-Y., Sangai, A., Gholipour, M., Chen, D.: Graphene nano-ribbon field-effect transistors as future low-power devices. Int. Symp. Low Power Electron. Design (ISLPED) (2013). https://doi.org/10.1109/islped.2013.6629286
Lin, J.-F., Sheu, M.-H., Hwang, Y.-T., Wong, C.-S., Tsai, M.-Y.: Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(11), 3033–3044 (2017). https://doi.org/10.1109/TVLSI.2017.2729884
Weste, N. H., Harris, D.: CMOS VLSI design: a circuits and systems perspective, 4th edn. Pearson (2011)
Phyu, M.W., Goh, W.L., Yeo, K.S.: A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. IEEE Int. Symp. Circuits Syst. (2015). https://doi.org/10.1109/ISCAS.2005.1465116
Harris, D.M.: Sequential element timing parameter definition considering clock uncertainty. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(11), 2705–2708 (2014). https://doi.org/10.1109/TVLSI.2014.2364991
Phyu, M. W.: Low-voltage low-power CMOS flip-flops. PhD Thesis, Nanyang Technological University 2009. https://doi.org/10.32657/10356/46774
Liu, Z., Kursun, V.: Characterization of a novel nine-transistor SRAM cell. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (2008). https://doi.org/10.1109/TVLSI.2007.915499
Prasad, G., Anand, A.: Statistical analysis of low-power SRAM cell structure. Analog Integr. Circ. Sig. Process 82(1), 349–358 (2015). https://doi.org/10.1007/s10470-014-0463-1
Almeida, R.B., Butzen, P.F., Meinhardt, C.: 16NM 6T and 8T CMOS SRAM cell robustness against process variability and aging effects. Symp. Integr. Circuits Syst. Design (SBCCI) (2018). https://doi.org/10.1109/sbcci.2018.8533253
Grossar, E., Stucchi, M., Maex, K., Dehaene, W.: Read stability and write-ability analysis of SRAM cells for nanometer technologies. IEEE J. Solid-State Circuits 41(11), 2577–2588 (2006). https://doi.org/10.1109/JSSC.2006.883344
Nayak, D., Acharya, D., Rout, P.K., Mahapatra, K.: Design of low-leakage and high stable proposed SRAM cell structure. Int. Conf. Electron Commun. Syst. (2014). https://doi.org/10.1109/ECS.2014.6892682
Predictive Technology Model. [Online]. Available: https://ptm.asu.edu/
Lim, W., Chin, H.C., Lim, C.S., Tan, M.L.P.: Performance evaluation of 14 nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis. J. Nanomater. 2014, 105 (2014). https://doi.org/10.1155/2014/820763
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The authors acknowledge funding support from Babol Noshirvani University of Technology through grant program No. BNUT/389023/98.
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Abbasian, E., Gholipour, M. A variation-aware design for storage cells using Schottky-barrier-type GNRFETs. J Comput Electron 19, 987–1001 (2020). https://doi.org/10.1007/s10825-020-01529-y
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DOI: https://doi.org/10.1007/s10825-020-01529-y