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Alloying conducting channels for reliable neuromorphic computing

Nature Nanotechnology volume 15, pages 574–579 (2020)Cite this article

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A Publisher Correction to this article was published on 23 June 2020

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Abstract

A memristor1 has been proposed as an artificial synapse for emerging neuromorphic computing applications2,3. To train a neural network in memristor arrays, changes in weight values in the form of device conductance should be distinct and uniform3. An electrochemical metallization (ECM) memory4,5, typically based on silicon (Si), has demonstrated a good analogue switching capability6,7 owing to the high mobility of metal ions in the Si switching medium8. However, the large stochasticity of the ion movement results in switching variability. Here we demonstrate a Si memristor with alloyed conduction channels that shows a stable and controllable device operation, which enables the large-scale implementation of crossbar arrays. The conduction channel is formed by conventional silver (Ag) as a primary mobile metal alloyed with silicidable copper (Cu) that stabilizes switching. In an optimal alloying ratio, Cu effectively regulates the Ag movement, which contributes to a substantial improvement in the spatial/temporal switching uniformity, a stable data retention over a large conductance range and a substantially enhanced programmed symmetry in analogue conductance states. This alloyed memristor allows the fabrication of large-scale crossbar arrays that feature a high device yield and accurate analogue programming capability. Thus, our discovery of an alloyed memristor is a key step paving the way beyond von Neumann computing.

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Fig. 1: The d.c. switching performance of a Si memristor with a Ag–Cu alloy.
Fig. 2: Kinetically and thermodynamically limited alloying effect on d.c. switching performance.
Fig. 3: Alloy effect on analogue nanosecond switching behaviours of Si memristors.
Fig. 4: 32 × 32 transistor-less Si memristor arrays with Ag and alloy active electrodes.

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The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

This work is partially supported by MIT Research Support Committee funds, MIT-IBM Watson AI Lab, Samsung Global Research Laboratory and NSF-SRC-E2CDA. We thank J. J. Yang and Q. Xia of the University of Massachusetts for valuable help and fruitful discussion. We acknowledge the Texas Advanced Computing Center (TACC) for providing computation sources. This work was performed in part at the Micro Technology Laboratories (MTL) at the Massachusetts Institute of Technology, and in part at the Harvard University Center for Nanoscale Systems (CNS).

Author information

Author notes

  1. These authors contributed equally: Hanwool Yeon, Peng Lin, Chanyeol Choi.

Authors and Affiliations

  1. Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA

    Hanwool Yeon, Peng Lin, Scott H. Tan, Yongmo Park, Doyoon Lee, Jaeyong Lee & Jeehwan Kim

  2. Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, USA

    Hanwool Yeon, Peng Lin, Chanyeol Choi, Scott H. Tan, Yongmo Park, Doyoon Lee, Jaeyong Lee & Jeehwan Kim

  3. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA

    Chanyeol Choi

  4. Institute of Microelectronics, Tsinghua University, Beijing, China

    Feng Xu, Bin Gao, Huaqiang Wu & He Qian

  5. Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley, CA, USA

    Yifan Nie

  6. IBM T. J. Watson Research Center, Yorktown Heights, NY, USA

    Seyoung Kim

  7. Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea

    Seyoung Kim

  8. Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA

    Jeehwan Kim

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Contributions

H.Y. and J.K. conceived this work and J.K. supervised the team. H.Y., P.L., C.C. and J.K. designed the experiments and prepared the manuscript. H.Y., P.L., C.C., S.H.T., Y.P. and D.L. performed the device fabrication. H.Y. and C.C. conducted the d.c. switching measurements. C.C., P.L., S.K. and Y.P. performed the pulse-switching measurements. P.L. performed the array measurements. H.Y., C.C., F.X., B.G., H.W., H.Q. and Y.N. performed and analysed the ab initio calculations and kinetic Monte Carlo simulations. All the authors discussed and contributed to the discussion and analysis of the results regarding the manuscript at all stages.

Corresponding author

Correspondence to Jeehwan Kim.

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Competing interests

The authors declare no competing interests.

Additional information

Peer review information Nature Nanotechnology thanks Wei Lu and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Extended data

Extended Data Fig. 1 Process flow of depositing Ag-Cu films for active metals.

We have design step-by-step metal deposition process to drive Ag-Cu together into switching medium on the stage of forming. We first deposited ultrathin Ag islands on switching medium, where the thickness of Ag islands determines the opening area of Si (step1). Next, we deposited ultrathin Cu on top of Ag islands-deposited Si where Cu islands make the direct contact with the switching medium (step2). Last, we encapsulated Ag-Cu islands with 15 nm thick Ag film (step3). The amount of Cu involved in switching is determined by ‘Ag-Cu thickness ratio’. The thicker Ag film is deposited, The less Cu is contributing to the switching. The Ag-Cu alloying conduction channels are formed in the switching medium during forming process.

Extended Data Fig. 2 Ag-Cu alloy formation.

Scanning electron microscopy (SEM) images and energy dispersive X-ray (EDX) mapping of Ag-Cu alloying film on amorphous Si surface. Scale bars: 400 µm. When the total thickness was 2 ~ 4 nm, discontinuous metal films were formed and the metal clusters were uniformly distributed. A merging of metal clusters was observed at 7-nm-thick Ag with 2-nm-thick Cu film Source data.

Source data

Extended Data Fig. 3 Ag-Cu alloying ratio effect on DC switching uniformity and retention.

Normalized on/off uniformity with respect to nominal thickness of (i) Ag and (ii) Cu layers. 15-nm-thick additional Ag layer was applied after the step-by-step evaporation. At each alloying condition, best-performed-device during 100 cycles at compliance current of 5 mA was selected for this mapping. Furthermore, DC switching curves with temporal on/off conductance variations and room temperature retention results are included. When Cu was evaporated even for 1 nm in advance to Ag, devices showed irreversible breakdown behavior that is similar results with pure Cu devices (20-nm-thick Cu layer). As Ag thickness increased under fixed Cu thickness (1 nm), switching performance dynamically modulated and Ag (2 nm)/Cu (1 nm) layers drove optimized switching performance: highly uniform switching with stable retention behavior at multi-level states. As Ag-Cu ratio was deviated from 2 nm-1nm, non-uniform switching with poor retention was observed (7 nm-1 nm) or on/off degradation occurred, although stable data retention was obtained (2 nm-2 nm). These results strongly suggest that Cu additives into Ag active electrode significantly affect the switching performance, even though the amount of Cu is too small to form continuous film on Si surface. Furthermore, the role of Cu can be summarized as follows. (1) Cu enhances stability of Ag-based conduction channel, but decreases maximum on/off ratio due to residual Cu elements bound to Si switching medium (called backbone of the conduction channel). (2) Excess Cu in Ag active electrode deteriorates on/off window with increasing cycle number. However, optimized Ag-Cu ratio can drive uniform switching with relatively stable data retention Source data.

Source data

Extended Data Fig. 4 Crossbar layout for alloy arrays with metal capping.

Metal capping for p+ Si bottom electrodes is preferred to reduce the line resistance in large array implementations. A new process was developed to make alloy array with gold capping layer. (a) formation of isolated a-Si/p+ Si line patterns on SOI wafer by photolithography and dry etching. The protrusions on the line patterns are active device areas. (b) capping Au on top of the p+ line patterns to reduce line resistance. The active areas remain intact. (c) passivation of the bottom electrodes while exposing the active areas. (d) patterning the top electrodes to finish device arrays.

Extended Data Fig. 5 Demonstration of the stability of Ag-Cu alloy memristor array for inference.

(a) four convolutional kernels shown in (b) were programmed into four columns of the 32 × 32 array for parallel kernel operation. Two memristors are used as differential pair to represent both positive and negative weights.

Supplementary information

Supplementary Information

Supplementary Notes 1–4, Figs. 1–21, Tables 1 and 2, Video 1 and refs. 1–39.

Supplementary Video 1

Kinetic Monte Carlo simulation of resistive switching dynamics based on a Ag–Cu alloy.

Source data

Source Data Fig. 1

Ag and Ag-Cu: DC switching curves, switching uniformity, and retention.

Source Data Fig. 2

Ag-Ti, Ag-Cr and Ag-Ni: DC switching curves, switching uniformity, and retention.

Source Data Fig. 3

Analogue switching performance of Ag and Ag-Cu devices.

Source Data Fig. 4

Image programming and convolutional kernel processing in Si memristor arrays.

Source Data Extended Data Fig. 2

Scanning electron microscopy (SEM) images and energy dispersive X-ray (EDX) mapping data of Ag-Cu film.

Source Data Extended Data Fig. 3

Ag-Cu alloying effect: DC switching curves, on/off uniformity, and retention.

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Yeon, H., Lin, P., Choi, C. et al. Alloying conducting channels for reliable neuromorphic computing. Nat. Nanotechnol. 15, 574–579 (2020). https://doi.org/10.1038/s41565-020-0694-5

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