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Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation

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Abstract

In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG-TFET) employing a metallic drain and a gate-drain underlap. The use of a metallic drain and an underlap results in complete ambipolar suppression in the proposed TFET. A 2D calibrated simulation studies have revealed that ambipolar current suppression of ~ 5 orders, without affecting the on-state current of the device, when the gate voltage is varied between 1 V and -1 V, is achieved in the proposed device in comparison to the conventional DG-TFET. The complete ambipolar reduction is attributed to the reduced band-to-band-tunneling (BTBT) rate because of the Schottky barrier formation at the channel/drain interface. Further, the use of gate/drain underlap suppresses the ambipolarity completely in the proposed device in comparison to the conventional one. An ON current (ION) and OFF current (IOFF) ratio (ION/IOFF) of ~ 1012 with a subthreshold slope (SS) of 63 mV/decade is achieved in the proposed device. Further, the effect of change of various parameters on the performance of the proposed device has been thoroughly studied. It has been observed that the performance can be optimized further by using the optimum value of these parameters. A process flow for the fabrication of the proposed device has also been given.

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References

  1. Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28(8):743–745

    Article  CAS  Google Scholar 

  2. Lu H, Seabaugh A (2014) Tunnel field-effect transistors: state-of-the-art. IEEE J ournal of the Electron Deviceces Society 2(4):44–49

    Article  Google Scholar 

  3. Mookerjea S, Datta S (2008) Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications, Device Research Conference, Santa Barbara, CA, pp. 47–48

  4. Boucart K, Ionescu AM (2007) Double gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733

    Article  CAS  Google Scholar 

  5. Cho S, Kang IM, Kamins TI, Park BG, Harris JS Jr (2011) Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation. Appl Phys Lett 99(243505):1–4

    Google Scholar 

  6. Zhou G et al (2012) Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180 μA/μm at VDS = 0.5 V, Electron Devices Meeting (IEDM), 2012 IEEE international, San Francisco, CA, pp. 32.6.1–32.6.4

  7. Koswatta SO, Koester SJ, Haensch W (2010) On the possibility of obtaining MOSFET-like performance and Sub-60-mV/dec swing in 1-D broken-gap tunnel transistors. IEEE Trans Electron Devices 57(12):3222–3230

    Article  CAS  Google Scholar 

  8. Krishnamohan T, Kim D, Raghunathan S, Saraswat K (2008) Double-gate strained-Ge Heterostructure tunneling FET (TFET) with record high drive currents and ≪60mV/dec subthreshold slope, 2008 IEEE International Electron Devices Meeting, San Francisco, CA, pp. 1–3

  9. Bashir F, Loan SA, Rafat M, Alamoud ARM, Abbasi SA (2015) A high-performance source engineered charge plasma-based Schottky MOSFET on SOI. IEEE Trans Electron Devices 62(10):3357–3364

    Article  CAS  Google Scholar 

  10. Bashir F, Loan SA, Rafat M, Alamoud ARM, Abbasi SA (2015) A high performance gate engineered charge plasma based tunnel field effect transistor. J Comput Electron 14(2):477–485

    Article  CAS  Google Scholar 

  11. Toh EH, Wang GH, Samudra G, Yeo YC (2008) Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. J Appl Phys 103(10):1–5

    Article  Google Scholar 

  12. Lattanzio L, Michielis LD, Ionescu AM (2012) The Electron-Hole Bilayer Tunnel FET. Solid-State Electron 74:85–90

    Article  CAS  Google Scholar 

  13. Ashita, Loan SA, Rafat M (2018) Ambipolar Leakage suppression in Electron-Hole Bilayer TFET: Investigation and Analysis. J Comput Electron 17(3):977–985

    Article  CAS  Google Scholar 

  14. Ashita S, Loan A, Rafat M (2018) A high-performance inverted-C tunnel junction FET with Source–Channel overlap pockets. IEEE Trans Electron Devices 65(2):763–768. https://doi.org/10.1109/TED.2017.2783764

    Article  CAS  Google Scholar 

  15. Garg S, Saurabh S (2018) Suppression of ambipolar current in tunnel FETsusing drain pocket: proposal and analysis. Superlattice Microst 113:261–270

    Article  CAS  Google Scholar 

  16. Shaker A, El Sabbagh M, El-Banna MM (2017) Influence of draindoping engineering on the ambipolar conduction and high-frequencyperformance of TFETs. IEEE Trans Electron Devices 64(9):3541–3547

    Article  CAS  Google Scholar 

  17. Anghel C, Hraziia A, Gupta AA, Vladimirescu A (2011) 30 nm tunnel FET with improved performance and reduced ambipolar current. IEEE Trans Electron Devices 58(6):1649–1654

    Article  CAS  Google Scholar 

  18. Piorox T , Vinet M et al (2009) Highly performant fully depeleted PMOSFET with ,metallic source/drain, in VLSI-TSA, pp. 88–89

  19. Wana J, Royer CL, Zaslavsky A, Cristoloveanu S (2011) Tunneling FETs on SOI: suppression of ambipolar leakage, low-frequency noise behavior, and modeling. Solid State Electron 65:226–233

    Article  Google Scholar 

  20. Rizwan M, Loan SA (2019) Drain-Engineered TFET with Fully Suppressed Ambipolarity for High Frequency Application. IEEE Trans Electron Devices 66(4):1628–1634

    Article  Google Scholar 

  21. Shih-Chieh Teng, Yen-So Su, and Yung-Hsien Wu (2019) Design and simulation of improved swing and Ambipolar effect for tunnel FET by band engineering using metal silicide at drain side IEEE transactions on nanotechnology, Volume 18,

  22. Kumar S, Loan SA, Alamoud AM (2016) Design of a novel high performance Schottky barrier based compact transmission gate. Superlattice Microst 92:337–347

    Article  CAS  Google Scholar 

  23. Loan SA, Kumar S, Alamoud AM (2016) Novel double gate metal source/drain Schottky MOSFET as an inverter. Accepted in Superlattices and Microstructures 91:78–89

    Article  CAS  Google Scholar 

  24. Vinet M et al (Aug. 2004) Self-aligned planar double-gate MOSFETs by bonding for 22-nm node, with metal gates, high-kappa dielectrics, and metallic source/drain. IEEE Electron Device Lett 30(7):565–567

    Google Scholar 

  25. Ashita S, Loan A, Rafat M (2019) Insights into the impact of pocket and source elevation in vertical gate elevated source tunnel FET structures. IEEE Trans Electron Devices 66(1):752–758. https://doi.org/10.1109/TED.2018.2878010

    Article  CAS  Google Scholar 

  26. Ehteshamuddin M, Loan SA, Alharbi AG, Alamoud AM, Rafat M (2019) Investigating a dual moscap variant of line-tfet with improved vertical tunneling incorporating fiqc effect. IEEE Trans Electron Devices 66(11):4638–4645. https://doi.org/10.1109/TED.2019.2942423

    Article  CAS  Google Scholar 

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi, 110025, India

    Anam Khan & Sajad A. Loan

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  1. Anam Khan
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  2. Sajad A. Loan
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Correspondence to Sajad A. Loan.

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Khan, A., Loan, S.A. Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation. Silicon 13, 1421–1431 (2021). https://doi.org/10.1007/s12633-020-00528-9

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  • DOI: https://doi.org/10.1007/s12633-020-00528-9

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