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Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices

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Abstract

Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By the use of HLS-based methodology, a number of approaches exists to facilitate development and to rapidly incorporate hardware accelerators into end-user applications. In this paper we present a generic SystemC behavioral model to generate efficient hardware LDPC decoders using Xilinx Vivado HLS. We evaluate the performance of provided architectures and assess efficiency over competing approaches. Hardware complexity reduction up to 10× are shown whereas the throughput speedups are between 1.5× and 16×. The provided architectures have performance in the same order of magnitude of handcrafted RTL architectures.

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Notes

  1. SystemC model of scalar and vector libraries and LDPC decoder sources will be released under open-source licence on GitHub after the publication of the paper.

  2. Both tasks can be performed in parallel to save\(\frac {N}{Z}\) clock cycles.

  3. Observed for 100 MHz and 300 MHz frequencies. This model solves \({\mathcal{M}}_{1}\) model pipeline flush penalties as shown in Gantt diagram Fig. 7.

  4. VHDL source code was modified for memory declarations

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Authors and Affiliations

  1. IMS laboratory-UMR 5218, Bordeaux-INP, Univ. of Bordeaux, 351, cours de la Libération, Talence, 33405, France

    Yann Delomier, Bertrand Le Gal, Jérémie Crenne & Christophe Jego

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  1. Yann Delomier
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  2. Bertrand Le Gal
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  4. Christophe Jego
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Correspondence to Bertrand Le Gal.

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Delomier, Y., Le Gal, B., Crenne, J. et al. Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices. J Sign Process Syst 92, 727–745 (2020). https://doi.org/10.1007/s11265-020-01519-0

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