Abstract
The results of the TCAD (Technology Computer Aided Design) simulation of 65-nm bulk CMOS combinational logical elements of a triple majority gate (TMG) for a reliable microprocessor redundant system are presented. The AND and the OR logic elements, each of which consists of NAND and NOR elements and pairs of inverters, topologically located before and after the line of transistors of each of NAND and of NOR elements, are more noise-immune to single transient processes under the impact of single ionizing particles due to the minimization of the duration of the noise pulse by partially compensating them during the simultaneous charge collection from the track of a single nuclear particle. In simulation with TCAD tools, the tracks of the particles along the normal to the chip surface are used. The charge collection by logical elements with compensation when a linear transfer of particle energy to the track of up to 60 MeV cm2/mg leads to a reduction of the duration of the pulse noise at the output of CMOS AND (and OR) elements by factors of 2 to 5.
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Funding
The reported study was funded by Russian Foundation for Basic Research (RFBR), project number 19-07-00651.
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Translated by M. Kromin
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Katunin, Y.V., Stenin, V.Y. Modeling of Single Ionizing Particle Impacts on Logical Elements of a CMOS Triple Majority Gate. Russ Microelectron 49, 214–223 (2020). https://doi.org/10.1134/S1063739720020043
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DOI: https://doi.org/10.1134/S1063739720020043