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A Compact Analytical Drain Current Model of Fully Depleted SOI MOSFETs with Lightly Doped N- underneath the N+ Source Region

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Abstract

In this work, we report a 2-D analytical model for threshold voltage and drain current of fully depleted silicon-on-insulator (SoI) metal oxide semiconductor field-effect transistor (MOSFET) with lightly doped N- underneath the N+ source region. This model considers the effect of oxide thickness, source doping variations and silicon film thickness. The accuracy of the proposed model is verified using 2-D numerical simulations in terms of surface potential, threshold voltage and drain current. In comparison with the conventional FD SOI devices, the proposed model predicts that modified source based FD SOI structure gives better OFF-state current, improved ON-state to OFF-state current (ION/IOFF ~ 109) ratio.

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Acknowledgements

This work is supported by the AICTE under research program scheme (RPS-60). Authors would like to thank incubation cell of IIT Kanpur for providing Sentaurus tool in VLSI/EDA lab.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, India

    Vimal Kumar Mishra

  2. Nanoelectronics and VLSI Lab, Indian Institute of Information Technology, Jabalpur, India

    Sunil Pandey

  3. Madan Mohan Malaviya University of Technology, Gorakhpur, India

    Nilesh Anand Srivastava & R. K. Chauhan

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  1. Vimal Kumar Mishra
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  2. Sunil Pandey
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  3. Nilesh Anand Srivastava
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  4. R. K. Chauhan
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Correspondence to Vimal Kumar Mishra.

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Mishra, V.K., Pandey, S., Srivastava, N.A. et al. A Compact Analytical Drain Current Model of Fully Depleted SOI MOSFETs with Lightly Doped N- underneath the N+ Source Region. Silicon 13, 1359–1365 (2021). https://doi.org/10.1007/s12633-020-00525-y

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