Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs
Introduction
The efficiency of automated test pattern generators (ATPG) and the test quality of logic Built-in Self-Test (BIST) rely heavily on the controllability of signals and testability of faults in circuits, and on the accuracy and speed of methods for calculation of the related measures.
Testability of digital circuits and systems, in general, is understood how difficult it is to test the system, measured in terms of the size required by test set to be complete [1]. The well-known measurable characteristics of testability are controllability and observability of signals in the circuit under test [2].
Whereas controllability denotes the ease with which a node within a circuit can be set to a logical value, the observability characterizes the ease of determining the erroneous change of the value of a node by observing the circuit's primary outputs. On the other hand, the observability is the function of controllability of signals activating the paths from the fault location to the point where the error is observable.
The results of testability analysis can be used for speeding up test generation, or for introducing changes into the design to improve its testability. For pseudorandom test, (e.g. logic BIST), the test quality is highly dependent on the testability. Here, the biggest problem is the low coverage of random pattern resistant faults (faults that have very low probability of detection by pseudorandom patterns). Controllability and observability measures can be used for placing additional test-points to improve the testability and achieve the required fault coverage.
The methods of measuring testability can be classified as heuristic, probabilistic and fault simulation based methods [2,3]. The heuristic methods, such as SCOAP, COP, CAMELOT, VICTOR [2,3], are circuit topology based. They have been found very helpful in off-line deterministic test generation for the given circuit represented at gate level. The assumption of independence of signals, converging at the same node of the circuit from the same fan-out node, limits the accuracy of these methods. This has led to the use of probabilistic definition of testability [4], [5], [6]. The probabilistic testability measures are useful in design of logic BIST circuits which generate pseudorandom test sequences on-line. For evaluating the probabilistic testability of circuits, and for calculating the pseudo-random test length which satisfies the requirements of test quality, the probabilistic analysis of circuits is needed. Such analysis is based on calculation of signal probabilities on the lines of circuits.
The mentioned heuristic and probabilistic methods are attractive because of the high speed. The calculated testability measures are also independent of the test patterns to be used for testing. However, these methods suffer from low accuracy. An alternative is the fault simulation based approach of testability evaluation, which allows achieving higher accuracy, but may require higher cost of computation.
This paper is devoted to the topic of probabilistic testability evaluation with main emphasis on signal probability calculation in the given digital circuit. A method is proposed, which allows increased accuracy of signal probability calculation at reasonable time cost of the calculation procedure.
The paper is organized as follows. In Section 2, an overview about the background and state-of-the-art of probabilistic testability analysis is given. Section 3 introduces the concept of modeling digital circuits with Structurally Synthesized BDDs (SSBDD), Section 4 discusses two basic approaches to signal probability calculation in digital circuits, and Section 5 presents the foundations of the new SSBDD based method. In Section 6 and 7, a discussion of the proposed method is presented. In Section 8, we extend the proposed probability calculation method for computing the observability of signals and testability of circuits. In Section 9, we show how the proposed method can be applied for identification of redundant and also hard-to-test faults. Section 10 presents experimental results, and Section 11 concludes the paper.
Section snippets
Overview about the state of the art
Beyond the test generation task, the problem of computing signal probabilities in circuits is important for a wider range of applications in the test field such as design for testability e.g. by insertion of test points, for evaluation of the impact of radiation-induced transient errors and for calculating the reliability measures for digital circuits.
Ad hoc methods of design for testability (DFT) [2,3] are based on insertion of test points to improve the controllability and observability of
Structurally Synthesized BDDs
This Section gives a definition of the SSBDD [35], [36], [37]. We use the graph theory notations instead of traditional ite (if-then-else) expressions [26] because all the procedures related to the manipulations on SSBDDs are based on the topological reasoning rather than on graph symbolic manipulations as is traditionally the case with BDDs.
Definition 1 Consider an SSBDD as a directed acyclic graph Gy = (M, Γ, X) for representing a Boolean expression y = F(X), where X – is the set of literals of the
The problem of calculating signal probabilities
Let us formulate the task of calculating signal probabilities in digital circuits as follows. Assume that each input xk of the given circuit, represented by a function y = F(X), where X is a vector X = x1, x2, …, xn, is characterized by the probability pk of having the signal xk = 1. The task is to calculate, using the given input probabilities pk, the probability py that the output of the circuit will also be y = 1. The ultimate goal will be not only to calculate the signal probability py for
Calculation of probabilistic controllability of signals in digital circuits using SSBDDs
In this Section, we propose a new method for calculating the signal probabilities for the given circuits using the SSBDD model and compare it with the state-of-the-art concepts discussed in the previous Section.
Definition 2 We call a full activated path l in SSBDD Gy = (M, Γ, X) a 1-path (or a 0-path) if it terminates in the terminal node #1 (or #0). The horizontal edges on this path are called 1-edges, and vertical edges are called 0-edges. A path l in SSBDD is considered as a set of nodes passed by this
Calculation of probabilistic controllability of signals for internal nodes of circuits
In Fig. 4 it was shown how the internal sub-circuits of a given circuit can be mapped into the SSBDD of the circuit as subgraphs of SSBDD. The problem, how to extract from a given SSBDD a subgraph which represents the desirable sub-circuit in the circuit represented by the SSBDD, was discussed in [42].
In Fig. 4b, there are 4 internal nodes shown, for which the values of probabilities pa, pb, pc, pd, in addition to the probability of the output signal py would be expected. For each node a
Discussion of the three approaches to signal probability calculation in digital circuits
The discussed three methods differ in the following aspects. Method 1 has linear complexity and hence is computing cost efficient, but suffers in losing the accuracy of results. Methods 2 provides exact results, but suffers in the cost of computations. The new Method 3 also provides exact results. It outperforms Method 1 and allows concurrent calculation of the probabilities of all structural signals in the given circuit. In comparison with Method 2, the new method is also more efficient, since
Using controllability calculation for estimating the testability of faults in circuits
Traditionally the testability of a fault f in terms of fault detection probability p(f) is calculated as the multiplication of the following probabilities [2]Here, p[act(f, x)] is the probability of activating the fault f to a selected node labelled by variable x, so that in case of the fault f, the value of x will change. The value of p[obs(x)] is the probability that the faulty signal of x is propagating to the output node y, where the test responses are observed.
Identification of redundant and hard-to-detect faults in digital circuits
Step 1 of Algorithm 1, which performs the tracing of all consistent 1-paths in a digital circuit, can also be used for identification of redundancies in digital circuits.
Let us have a Boolean function y = F(X) represented in Fig. 13a as SSBDD, which is the same as the SSBDD in Fig. 5b for the circuit in Fig. 5a. In this circuit, there are three redundant faults related to the AND gate with inputs x12 and x32. Let us insert into the SSBDD model of the circuit one of these faults, e.g. x12 0.
Experimental results
The goals of experimental research were twofold: to investigate and compare the accuracy of calculating signal probabilities, and the speed of calculations between two models of combinational circuits: the plain gate-level networks, and the higher macro-level networks with FFR-modules as macros. Experiments were carried out with Intel Core i5 3570 Quad Core 3.4 GHz, 8 GB RAM.
To compare the accuracy of calculated probabilities, we compared two approaches:
- (1)
gate-level approach, where the full
Conclusions
In this paper, a novel method, based on the SSBDD theory, for calculating signal probabilities as controllability measures for combinational circuits was proposed.
The main contribution of the paper, compared to state-of-the-art, is twofold: a novel technique to speed up the computation process, and a technique, which allows increasing the accuracy of calculated probabilities. The speed-up of the probability calculation is achieved due to reducing the complexity of the computation model by
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgment
The work has been supported in part by project H2020 MSCA ITN RESCUE (EU Horizon 2020, Grant 722325), Estonian research grant IUT 19-1 and Excellence Centre EXCITE in Estonia. We thank the reviewers for the useful comments.
Maksim Jenihhin is a professor of Computing Systems Reliability at the Department of Computer Systems of Tallinn University of Technology. He holds M.Sc. and Ph.D. degrees in Computer Engineering from Tallinn University of Technology (2004 and 2008 respectively). His research interests include methodologies and EDA tools for hardware design, verification and debug as well as nanoelectronics reliability and manufacturing test topics. Maksim is a project coordinator for H2020 RESCUE -
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2022, Microelectronics ReliabilityCitation Excerpt :If the monitoring parameters related to diagnosis are ignored, the fault diagnosis technology will fail to achieve an accurate fault diagnosis [12]. Products with excellent testability can effectively carry out performance monitoring and fault diagnosis to speed up test generation [13], reduce the time of detection and fault isolation, save life cycle cost [14,15], reduce the technical requirements for maintenance workers, and improve task reliability and efficiency [16–19]. The dependency matrix (D matrix) is an important diagnostic strategy information retrieved from testability modelling and analysis, wherein the relation between faults and tests in a system can be described by the logical value [20].
Maksim Jenihhin is a professor of Computing Systems Reliability at the Department of Computer Systems of Tallinn University of Technology. He holds M.Sc. and Ph.D. degrees in Computer Engineering from Tallinn University of Technology (2004 and 2008 respectively). His research interests include methodologies and EDA tools for hardware design, verification and debug as well as nanoelectronics reliability and manufacturing test topics. Maksim is a project coordinator for H2020 RESCUE - Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design.
Jaan Raik is a professor of Digital Systems Verification at the Department of Computer Systems of Tallinn University of Technology and the leader of the Center for Dependable Computing Systems Design (DCSD). Prof. Raik received his M.Sc. and Ph.D. degrees in Computer Engineering from Tallinn University of Technology in 1997 and in 2001, respectively. He is a member of IEEE Computer Society, HiPEAC and a member of steering/program committees of several conferences. He has co-authored more than 200 scientific publications.
Raimund Ubar is a professor at Tallinn University of Technology, and Head of the Centre for Integrated Electronic Systems and Biomedical Engineering in Estonia. He received PhD degree in 1971 from the Bauman Technical University in Moscow, and DSc degree in 1987 from the Latvian Academy of Sciences. His scientific interests include computer science, design for testability and diagnostics of technical systems. Ubar is a member of Estonian Academy of Sciences, and Golden Core member of IEEE Computer Society.
Lembit Jürimägi is a lecturer at Tallinn University of Technology. He received his M.Sc. degree in Computer Engineering in 2008 and is currently finishing his Ph.D. studies at Tallinn University of Technology. His scientific interests include modeling, simulation and testing of digital circuits.