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Design of low-power CMOS transceiver front end for 2.4-GHz WPAN applications

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Abstract

This paper describes the design of low-power direct conversion transceiver front end for WPAN (Wireless Personal Area Network) applications using TSMC 0.13 µm CMOS technology. Subharmonic mixers are proposed to mitigate the drawbacks of DC offset problem in direct conversion receiver and injection locking problem in direct conversion transmitter. The receiver front end comprises a low-noise amplifier (LNA), balun and subharmonic mixer. The direct conversion transmitter front end adopts a subharmonic passive mixer, differential to single-ended converter, driver and power amplifier. The post-layout simulation results produce voltage gain of 29 dB, noise figure of 5.84 dB, IIP3 of − 12 dBm and 1.79 mW consumption power for receiver front end at a supply voltage of 0.8 V. The transmitter front end achieves conversion gain of 15 dB, 0 dBm output 1-dB compression point (OP1dB) and 4.27 mW power consumption.

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Abbreviations

CG:

Conversion gain

P LO :

Local oscillator power

OP-1:

Output 1-dB compression point

IIP3:

Input 3rd-order intercept point

ω LO :

Local oscillator frequency

P DC :

DC power consumption

S(2,2):

Output return loss

S(1,1):

Input return loss

NF:

Noise figure

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Authors and Affiliations

  1. Rajalakshmi Institute of Technology, Kuthambakkam Post, National Highway 4, Chembarambakkam, Chennai, 600124, Tamil Nadu, India

    S Manjula

  2. Mepco Schlenk Engineering College, Sivakasi, India

    D Selvathi

  3. RFIC Technologies, ST Johns’ Road, Ulsoor, Bangalore, 560042, India

    Suchitav Khadaganga

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  1. S Manjula
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  2. D Selvathi
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  3. Suchitav Khadaganga
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Correspondence to S Manjula.

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Manjula, S., Selvathi, D. & Khadaganga, S. Design of low-power CMOS transceiver front end for 2.4-GHz WPAN applications. Sādhanā 45, 131 (2020). https://doi.org/10.1007/s12046-020-01365-7

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  • DOI: https://doi.org/10.1007/s12046-020-01365-7

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