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Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

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Abstract

In this paper, a new design of low power, high performance Radix-4 MBW multiplier unit has been described. The low power performance has been achieved by dynamic voltage scaling. Based on CCGDI technique which reduces the switching activity and output capacitance, the proposed multiplier unit has been designed by utilizing three different low power methodologies i.e., reduction in output capacitance and switching activity along with biasing voltage reduction. In order to reduce the number of transistor and delay, here GDI based parallel adders are used in the Wallace tree counters. The multiplier has been implemented with constant threshold voltage PTM 45 nm devices technology and simulated in standard CAD tool simulator for 4, 8 and 16 bit operand multiplications. The proposed design consumes 238.98 µw average power and it has a propagation delay of 2.458 ns for 16 × 16 bit multiplications at speed 100 MBps which is 47% better in terms of power-delay-product than counter based GDI Wallace tree multiplier structure.

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Abbreviations

CAD:

Computer aided design

CCGDI:

Cyclic Combinational Gate Diffusion Input

CMOS:

Complementary Metal Oxide Semiconductor

DA:

Distributive Arithmetic

DSP:

Digital Signal Processing

DVS:

Dynamic Voltage Scaling

EDA:

Electronic Design Automation

FA:

Full Adder

FF:

Fast nmos Fast pmos

FIR:

Finite Impulse Response

FPGA:

Field Programmable Gate Array

GDI:

Gate Diffusion Input

HA:

Half Adder

LS:

Level Shifter

MAC:

Multiplier and Accumulator

MBW:

Modified Booth Wallace

MEMS:

Micro Electro Mechanical Systems

PDP:

Power Delay Product

PPG:

Partial Product Generators

PTM:

Predictive Technology Model

PVT:

Process Voltage Temperature

SS:

Slow nmos Slow pmos

TT:

Typical Transistor

References

  1. Kumar M A, Rao O R, Dileep M, Reddy C V P Rand Mani K P 2016 Performance Evaluation of Different Multipliers in VLSI using VHDL. International Journal of Advanced Research in Computer and Communication Engineering 5: 6–11

    Google Scholar 

  2. Lamba Band Sharma A 2018 A review paper on different multipliers based on their different performance parameters In: Proceedings of the 2nd International Conference on Inventive Systems and Control (ICISC) : pp. 324–327

  3. Carbognani F, Buergin F, Felber N, Kaeslin H and Fichtner W 2008 A low-power transmission-gate-based 16-bit multiplier for digital hearing aids. Analog Integrated Circuit and Signal Processing 56: 5–12

    Article  Google Scholar 

  4. Xue H, Patel R, Boppana N V V K and Ren S 2018 Low-power-delay-product radix-4 8*8 Booth multiplier in CMOS. Electronics Letter 54: 344–346

    Article  Google Scholar 

  5. Colón-Bonet G andWinterrowd P 2008 Multiplier Evolution: A Family of Multiplier VLSI Implementations. The Computer Journal 51: 585–594

    Article  Google Scholar 

  6. Jiang H, Han J, Qiao F and Lombardi F 2016 Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation. IEEE Transactions on Computers 65: 2638–2644

    Article  MathSciNet  Google Scholar 

  7. Rabaey J M, Chandrakasan A and Nikolic B 2002 A Historical Perspective, Digital Integrated Circuits, A Design Perspective, 2nd Edition, Englewood Cliffs, New Jersey : Prentice Hall, pp. 10–20

    Google Scholar 

  8. Morgenshtein A, Fish A and Wagner I A 2002 Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits. IEEE Transaction on VLSI Systems 10: 566–581

    Article  Google Scholar 

  9. Mukherjee B, Roy B, Biswas A and Ghosal A 2015 Cyclic combinational gate diffusion input (CCGDI) technique-a new approach of low power digital combinational circuit design In: Proceedings of the IEEE Int. Conf. on Electrical, Computer and Communication Technologies (ICECCT): pp. 1–6

  10. Burd T and Brodersen R W 2002 Circuit Design Methodology, Energy Efficient Microprocessor Design, Boston: Springer: pp. 79–124

    Book  Google Scholar 

  11. Zhao W, Alvarez A B and Ha Y 2015 A 65-nm 25.1-ns 30.7-fJ robust subthreshold level shifter with wide conversion range. IEEE Transaction on Circuits Syst. II, Exp. Briefs. 62: 671–675

    Google Scholar 

  12. Mohanty S P, Kougianos E and Okobiah O 2012 Optimal Design of a Dual-Oxide Nano-CMOS Universal Level Converter for Multi-VddSoCs. Springer Analog Integrated Circuits and Signal Processing Journal 72: 451–467

    Article  Google Scholar 

  13. Wen L, Cheng X, Tian S, Wen H and Zeng X 2016 Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. IEEE Trans. Circuits Syst. II, Exp. Briefs. 63: 346–350

    Google Scholar 

  14. Lanuzza M, Crupi F, Rao S, Rose R D, Strangio S and Iannaccone G 2017 An Ultralow-Voltage Energy-Efficient Level Shifter. IEEE Trans. on Circuits Syst. II, Exp. Briefs. 64: 61–65

    Google Scholar 

  15. Hosseini S R, Saberi M and Lotfi R 2017 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications. IEEE Trans. on VLSI Systems 25: 1154–1158

    Article  Google Scholar 

  16. Mukherjee B, Roy B, Biswas A and Ghosal A 2015 Design of a Low Power 4x4 Multiplier Based on Five Transistor (5-T) Half Adder, Eight Transistor (8-T) Full Adder and Two Transistor (2-T) AND Gate. In: Proceedings of the Third International Conference on Computer, Communication, Control and Information Technology (C3IT): pp. 1-5

  17. Mukherjee B and Ghosal A 2018 Design and Analysis of a Low Power High-Performance GDI Based Radix 4 Multiplier Using Modified Booth Wallace Algorithm In: Proceedings of the 1st IEEE Electron Device Kolkata Conference (EDKCON-2018) : pp. 247–251

  18. Mukherjee B and Ghosal A 2019 Design and Implementation of Low Power, High Speed, Area Efficient Gate Diffusion Input Logic Based Modified Vedic Multiplier for Digital Signal Processor. International Journal Innovative Knowledge Concept 7: 243–250

    Google Scholar 

  19. Mukherjee B and Ghosal A 2019 Counter Based Low Power, Low Latency Wallace Tree Multiplier Using GDI Technique for On-chip Digital Filter Applications In: Proceedings of the 3rd International Conference on Devices for Integrated Circuits (DevIC-2019): pp. 151–155

  20. Mukherjee B and Ghosal A 2019 Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor. Journal of Micromechanics and Microengineering 29: 064003

    Article  Google Scholar 

  21. Reddy K M, Vasantha M H, Nithin K Y B and Dwivedi D 2019 Design and analysis of multiplier using approximate 4-2 compressor. AEU - International Journal of Electronics and Communications 107: 89–97

    Article  Google Scholar 

  22. Asif S and Kong Y 2015 Design of an Algorithmic Wallace Multiplier using High Speed Counters, In: Proceedings of the Tenth International Conference on Computer Engineering & Systems (ICCES), Cairo: pp. 133–138

  23. Saha A, Pal R, Naik A G and Pal D 2018 Novel CMOS multi-bit counter for speed-power optimization in multiplier design. AEU-International Journal of Electronics and Communications 95: 189–198

    Article  Google Scholar 

  24. Zhang X, Boussaid F and Bermak A 2014 32 Bit × 32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler. IEEE Transactions on VLSI Systems 22: 759–770

    Article  Google Scholar 

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Authors and Affiliations

  1. Neotia Institute of Technology, Management and Science, Diamond Harbour Road, South 24 Parganas, Kolkata, India

    Biswarup Mukherjee

  2. Institute of Radio Physics and Electronics, University of Calcutta, Kolkata, India

    Aniruddha Ghosal

Authors
  1. Biswarup Mukherjee
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  2. Aniruddha Ghosal
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Correspondence to Biswarup Mukherjee.

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Mukherjee, B., Ghosal, A. Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications. Sādhanā 45, 119 (2020). https://doi.org/10.1007/s12046-020-01340-2

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  • DOI: https://doi.org/10.1007/s12046-020-01340-2

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