Abstract
This work presents Memphis, which comprises a flexible EDA framework and a many-core model for heterogeneous SoCs. The framework, together with the many-core model supports the integration of processors, network interfaces, routers, and peripherals. A set of tools enable a decoupled generation and compilation of the hardware, operating systems, and applications. The hardware model is cycle-accurate, with a SystemC model to speed up simulation time and a VHDL model enabling prototyping in FPGAs devices. The framework provides a rich set of graphical debugging tools enabling an easy and intuitive understanding of computation and communication events happening at runtime. The coupled integration of the platform model to the EDA framework makes Memphis well suited to be employed in research and teaching. As case studies, we provide a set of evaluations addressing the many-core generation, simulation, and debugging. Different applications sets were employed, enabling to characterize the computation and communication performance of the many-core, as well as, evaluate an AES encryption application performance according to different levels of parallelism.
Similar content being viewed by others
References
Balkind J, McKeown M, Fu Y, Nguyen T, Zhou Y, Lavrov A, Shahrad M, Fuchs A, Payne S, Liang X, Matl M, Wentzlaff D (2016) OpenPiton: An open source manycore research framework. In: ASPLOS, pp 217–232. https://doi.org/10.1145/2954679.2872414
Busseuil R, Barthe L, Almeida GM, Ost L, Bruguier F, Sassatelli G, Benoit P, Robert M, Torres L (2011) Open-scale: a scalable, open-source NOC-based MPSoC for design space exploration. In: RECONFIG, pp 357–362. https://doi.org/10.1109/ReConFig.2011.66
Carara E, Moraes FG (2008) Deadlock-free multicast routing algorithm for wormhole-switched mesh networks-on-chip. In: ISVLSI, pp 341–346. https://doi.org/10.1109/ISVLSI.2008.18
Carara EA, de Oliveira RP, Calazans NLV, Moraes FG (2009) HeMPS—a framework for NoC-based MPSoC generation. In: ISCAS, pp 1345–1348. https://doi.org/10.1109/ISCAS.2009.5118013
Carvalho E, Marcon C, Calazans N, Moraes F (2009) Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs. In: SOC, pp 87–90. https://doi.org/10.1109/SOCC.2009.5335672
Castilhos G, Mandelli M, Madalozzo G, Moraes F (2013) Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes. In: ISVLSI, pp 153–158. https://doi.org/10.1109/ISVLSI.2013.6654651
Cheung N, Parameswaran S, Henkel J (2003) INSIDE: instruction selection/identification & design exploration for extensible processors. In: ICCAD, pp 291–297. https://doi.org/10.1109/ICCAD.2003.159703
Elmohr MA, Eissa AS, Ibrahim M, Khamis M, El-Ashry S, Shalaby A, AbdElsalam M, El-Kharashi MW (2018) RVNoC: a framework for generating RISC-V NoC-based MPSoC. In: PDP, pp 617–621. https://doi.org/10.1109/PDP2018.2018.00103
Hassan M (2018) Heterogeneous MPSoCs for mixed-criticality systems: challenges and opportunities. IEEE Des Test 35(4):47–55. https://doi.org/10.1109/MDAT.2017.2771447
Iniewski K (2012) Embedded systems: hardware, design, and implementation, 1st edn. Wiley, Hoboken
Intel: Intel’s New Mesh Architecture: The ‘Superhighway’ of the Data Center (2018). https://itpeernetwork.intel.com/intel-mesh-architecture-data-center/
Jiang N, Becker DU, Michelogiannakis G, Balfour J, Towles B, Shaw DE, Kim J, Dally WJ (2013) A detailed and flexible cycle-accurate Network-on-Chip simulator. In: ISPASS, pp 86–96. https://doi.org/10.1109/ISPASS.2013.6557149
Liu J (2000) Real-time system. Prentice Hall, Englewood Cliffs
Martin MMK, Sorin DJ, Beckmann BM, Marty MR, Xu M, Alameldeen AR, Moore KE, Hill MD, Wood DA (2005) Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput Arch News 33(4):92–99. https://doi.org/10.1145/1105734.1105747
Mellanox: TILE-Gx Processors (2018) http://www.mellanox.com/repository/solutions/tile-scm/docs/UG130-ArchOverview-TILE-Gx.pdf
Molanes RF, Amarasinghe K, Rodriguez-Andina J, Manic M (2018) Deep learning and reconfigurable platforms in the internet of things: challenges and opportunities in algorithms and hardware. IEEE Ind Electron Mag 12(2):36–49. https://doi.org/10.1109/MIE.2018.2824843
Monemi A, Tang J, Palesi M, Marsono M (2017) ProNoC: a low latency network-on-chip based many-core system-on-chip prototyping platform. Microprocess Microsyst 54:60–74. https://doi.org/10.1016/j.micpro.2017.08.007
Moraes FG, Calazans N, Mello A, Möller L, Ost L (2004) HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integration 38(1):69–93. https://doi.org/10.1016/j.vlsi.2004.03.003
Muthukaruppan TS, Pricopi M, Venkataramani V, Mitra T, Vishin S (2013) Hierarchical power management for asymmetric multi-core in dark silicon era. In: DAC, pp 1–9. https://doi.org/10.1145/2463209.2488949
Quan W, Pimentel AD (2016) A hierarchical run-time adaptive resource allocation framework for large-scale MPSoC systems. Des Autom Embed Syst 20(4):311–339. https://doi.org/10.1007/s10617-016-9179-z
Rahmani AM, Haghbayan MH, Miele A, Liljeberg P, Jantsch A, Tenhunen H (2017) Reliability-aware runtime power management for many-core systems in the dark silicon era. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(2):427–440. https://doi.org/10.1109/TVLSI.2016.2591798
Rhoads S (2016) Plasma CPU Core. https://opencores.org/project/plasma
Ruaro M, Chamorra H, Rubin F, Amory A, Moraes FG (2016) A data extraction and debugging framework for large-scale MPSoCs. In: ICECS, pp 616–619. https://doi.org/10.1109/ICECS.2016.7841277
Ruaro M, Lazzarotto FB, Marcon CA, Moraes FG (2016) DMNI: a specialized network interface for NoC-based MPSoCs. In: ISCAS, pp 1202–1205. https://doi.org/10.1109/ISCAS.2016.7527462
Ruaro M, Moraes FG (2016) Dynamic real-time scheduler for large-scale MPSoCs. In: GLSVLSI, pp 341–346. https://doi.org/10.1145/2902961.2903027
Ruaro M, Moraes FG (2017) Demystifying the cost of task migration in distributed memory many-core systems. In: ISCAS, pp 1–4. https://doi.org/10.1109/ISCAS.2017.8050257
Singh AK, Shafique M, Kumar A, Henkel J (2013) Mapping on multi/many-core systems: survey of current and emerging trends. In: DAC, pp 1–10. https://doi.org/10.1145/2463209.2488734
Skalicky S, Schmidt AG, Lopez S, French M (2015) A unified hardware/software MPSoC system construction and run-time framework. In: DATE, pp 301–304. https://doi.org/10.7873/DATE.2015.0097
Xu J, Wolf W, Henkel J, Chakradhar S, Lv T (2004) A case study in networks-on-chip design for embedded video. In: DATE, pp 770–775. https://doi.org/10.1109/DATE.2004.1268973
Zhang Q, Zhou M, Chen J, Yang H (2015) A homogeneous many-core x86 processor full system framework based on NoC. In: ICCSNT, pp 794–797. https://doi.org/10.1109/ICCSNT.2015.7490861
Acknowledgements
This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001. Fernando Gehm Moraes is supported by FAPERGS (17/2551-0001196-1) and CNPq (302531/2016-5), Brazilian funding agencies. Luciano L. Caimi and Vinicius Fochi are supported by CAPES (184993/2018-00, 184851/2018-00). Marcelo Ruaro is supported by CAPES/FAPERGS (88887.196173/2018-00).
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Ruaro, M., Caimi, L.L., Fochi, V. et al. Memphis: a framework for heterogeneous many-core SoCs generation and validation. Des Autom Embed Syst 23, 103–122 (2019). https://doi.org/10.1007/s10617-019-09223-4
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10617-019-09223-4