Reconfigurable FET-Based SRAM and Its Single Event Upset Performance Analysis Using TCAD Simulations
Introduction
Reconfigurable FET (RFET) achieves both P and N type transistor operations on the same device. Apart from the regular gate (known as control gate), we have program gates to perform the reconfigurable operation. RFET extends the principle of Schottky barrier MOSFET (SBMOSFET). SBMOSFET does not have heavily doped source-drain semiconductor regions like the conventional MOSFETs, instead they use Schottky metal contacts. Absence of source drain regions offers advantages like, (i) better scalability (ii) low parasitic source-drain resistance, and (iii) low temperature source-drain processing [1]. While in the SBMOSFET gate is used to control the drain current, in the RFET one gate is used to control the current flow and another gate is used to reconfigure the device as N or P type. Since RFET is derived from SBMOSFET, the above mentioned benefits of SBMOSFET are also applicable for RFET. The concept of RFET was introduced in the year 2008 [2] as a nano wire structure, and in the year 2011, André Heinzig et al. have reported TCAD simulation of Reconfigurable Silicon nano wire transistor [3]. The planar RFET was reported in the year 2011 by Frank Wessely et al. [4]. Three different RFET realizations are given in Ref. [5], depending upon the number of program gates, (i) single program gate and (ii) double program gates. Even though RFET has many advantages, it suffers from low drive current [5]. Reconfiguration is achieved by changing the polarity of the voltage applied to the program gate terminal, and thus we need both positive and negative bias for RFET operation [5]. The planar RFET reported in Ref. [5] uses two program gates, and is used in this study.
Fig. 1. Nano wire RFET-based digital gates, and single bit adder have been reported in the literature [6]. RFET based TSPC Flip-Flops, and conditional carry adder have also been studied [7,8].
Reconfigurable ALU based on DGCNTFET transistor is investigated in Ref. [9] Ionizing heavy ions upon interacting with the semiconductors produce mobile charge carriers, electrons and holes resulting in single event transient (SET) [10]. The damages produced by the SET pulse could be temporary or permanent. The temporary damage is known as soft error, and the permanent damage is hard error [11]. In the former case, the electronic device or the system can be put into working condition after the radiation strike but in the latter case typically the system fails to work after the strike. For example, when the radiation strikes a SRAM memory cell, the contents of the memory cell may be lost/changed, known as single event upset (SEU) and in this case the memory cell is still useable but the information is lost. Even though the soft errors are temporary, the consequences could be jeopardizing. Therefore, soft errors should be treated seriously. SEU is characterized by the minimum energy required to flip the content of a SRAM cell, known as critical dose. More the critical dose betters the cell’s immunity towards the radiation strike. SEU performance of the CMOS-based SRAM cells has been studied extensively in the literature [12]. Continuous scaling of CMOS devices reduces the critical dose. FinFET-based SRAM cells show better SEU performance compared to MOSFET-based SRAM cells [13]. SEU reports on junctionless device-based SRAM are available in Ref. [14].
The first contribution of this work is the realization of the SRAM cell operation using identical RFET devices i.e. there is no distinction between N and P devices. Here the regular SRAM parameters, read, write and hold SNMs(static noise margin) are extracted to characterize the SRAM cell. In the second contribution, we have investigated the SEU performance of the RFET-based.
SRAM cell by extracting critical dose. Both the works use numerical simulations, Sentaurus TCAD simulator. We have investigated the sensitive location within the device.
The structure of the RFET and its specifications, device simulation models, and transfer characteristics are discussed in section 2. Section 3 discusses the RFET based 6 T SRAM cell. Section 4 reports the soft error analysis of the discrete RFET device, and RFET-based SRAM cell. Section 5 provides the SNM and SEE (single event effects) comparison of RFET-based SRAM with other SRAMs. The conclusions are given in section 6.
Section snippets
Device structure and calibration of RFET
In this section, the device used to design the SRAM cell is calibrated against the already reported results in the literature, using numerical device simulations. We have chosen the planar RFET structure for our study. The device dimensions and other parameters from Ref. [5] are used to generate the device. structure, and to reproduce the ID-VG characteristics in our simulations. Table 1 provides the dimensions, doping and gate electrode work functions used in the study. The TCAD generated
RFET based 6 T SRAM cell
In this section, a RFET based 6 T-SRAM cell operation and its SNM are analyzed. The calibrated device discussed in section 2, has been used to build SRAM cell.
The 6 T SRAM cell circuit shown in Fig. 3(a) is realized using six identical RFET devices (the device is depicted in Fig. 1), and is called RFET-based SRAM. Fig. 3(b) presents the realization of RFET-based SRAM cell. All the six devices are identical and use a channel width of 30 nm. As already stated the devices are made to work as N
Soft error performance of RFET device and RFET based SRAM cell
In this section, the impact due to heavy ion radiation is studied. This section is divided into two subsections, (i) SET performance of a discrete RFET device, and (ii) SEU performance of a RFET-based SRAM cell. The SEE simulation is a transient simulation, and is done by invoking the heavy ion models apart from the regular device simulation models. Striking location, radiation dose (measured using linear energy transfer - LET in terms of MeV/mg/cm2), direction of hit (incident angle), the
Comparison with other technologies
In this section, RFET SRAM SNM values are compared with the other SRAMs available in the literature. Similarly, the SEE performance of RFET SRAM is also compared with the available studies in the literature. The SNM (Static noise margin) of FDSOI SRAM and CMOS SRAM are compared with proposed RFET SRAM, and is given in Table 5. The SNM values of RFET SRAM are comparable with the other SRAMs.
Table 6 provides the SET (collected charge) and SEU (threshold LET dose) comparison of FDSOI SRAM, CMOS
Conclusion
RFET device can be programmed to operate in N or P mode by applying suitable bias at its program gates. In this communication, we have demonstrated the 6 T RFET-based SRAM operation using six identical RFET devices using numerical device simulations. Both RFET and the proposed RFET SRAM have been studied for their single event effects. The RFET SRAM is compared with CMOS SRAM. The drawbacks of the RFET SRAM are (i) The RFET SRAM cell will certainly increase the cell footprint. (ii) The voltage
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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