TCAD simulation of hot-carrier stress degradation in split-gate n-channel STI-LDMOS transistors
Introduction
High-voltage lateral double diffused MOS transistors (LDMOS) are of great interest as they are needed for a variety of applications and can be easily integrated in smart power technologies. One of the key challenges in building this kind of devices is given by their reliability. The scaling of LDMOS devices inevitably leads to high-field issues, thus charge injection and hot carrier stress degradation mechanisms are identified to be the driving forces of device degradation. Moreover, nitrided gate oxides affect the long-term reliability [1] and, for high-voltage devices, the use of shallow-trench isolation (STIs) in the active region of the device would require an optimization accounting for degradation [2].
Previous studies on rugged LDMOS devices with STI structures mainly focused on the device characterization and optimization [3,4] and some works addressed recently the hot-carrier stress (HCS) analysis [2,[5], [6], [7]].
The high electric fields lead to the generation of interface traps in the proximity of the silicon/oxide interface within the drift region. This causes the shift of the electrical parameters (e.g., the on-resistance, RON) limiting the device lifetime.
The implementation of gate field-plate is a strategy in the design of integrated high-voltage LDMOS in order to improve the time-zero breakdown and the HCS performance of the device. Several gate field-plate architectures have been proposed [4,[8], [9], [10]] including grounded [9] and independently-biased [4] gate field-plate, each one addressing one or more figures of merit of the device. The introduction of a secondary gate has been proved to be a good technique [4,5,10] in order to reduce the HCS degradation effects and, being characterized by a lower gate capacity with respect to continuous gate architectures, it might be used to improve the dynamical behavior [9]. The primary function of the secondary gate is to help the depletion of the drift region of the device reducing the superficial electric field and decreasing the impact-ionization generation rate around the STI edge near the channel side during stress, while maintaining a high blocking voltage.
In this work, a TCAD investigation of the HCS degradation in n-channel split-gate LDMOS transistors designed for a nominal operating voltage of 40 V is proposed. In particular, the on-resistance degradation in linear regime has been experimentally investigated for different split-gate biases and stress conditions and reproduced by means of TCAD simulations using degradation models [6] implemented into the framework of the TCAD tool. Consequently, a detailed analysis of the electron distribution functions at different stress biases and of the interface trap generation rates has been carried out aiming at obtaining a deeper insight on the role played by hot-electrons in the HCS degradation mechanisms of the device under test.
Section snippets
Device structure and experiments
The n-channel split-gate transistor featuring a shallow trench isolation (STI) structure, schematically shown in Fig. 1, is realized in a 90 nm Bipolar-CMOS-DMOS (BCD) mixed technology by STMicroelectronics and designed for a nominal operating voltage of 40 V. The 12 nm-thick gate oxide is designed for operation at a maximum gate voltage VGS = 5 V. The poly-Si gap (the spacing between the two poly-Si gates) is the minimum spacing compatible with VGS.
The analysis of hot-carrier effects on the
Fresh characteristics analysis
First of all, 2D simulations of the device cross-sections have been carried out to fully investigate the behavior. The impurity concentration within the cross section has been inferred from process simulation results. Numerical simulations have been carried out using the drift-diffusion transport model with default parameters for the adopted physical models. The comparison of simulation results with measured turn-on characteristics in linear regime with different split-gate biases at room
TCAD analysis of hot-carrier stress degradation
Concerning HCS degradation, simulations have been performed using the Hot Carrier Stress degradation model implemented in the Synopsis TCAD tool [13] in order to reproduce the on-resistance shift as a function of the stress time by directly using the simulation tool.
By following [6], three different competing mechanisms such as single-particle (SP), multiple-particle (MP) and field-enhanced thermal interaction (TH) might contribute to the bond breaking at the Si/SiO2 interface. Thermal-induced
Conclusion
The role played by hot-electrons in the Hot-Carrier degradation mechanisms of a split-gate n-type LDMOS device featuring an STI structure has been extensively investigated by using TCAD models available in Synopsys TCAD tool. The TCAD has been proved to be a useful tool in order to quantitatively describe the role played by two HC degradation competing mechanisms, such as SP and MP, and to gain a deeper insight on which are points of the silicon/oxide interface where the degradation effects are
CRediT authorship contribution statement
Federico Giuliano: Conceptualization, Investigation, Formal analysis, Writing - original draft. Paolo Magnone: Investigation, Writing - original draft, Writing - review & editing.Simone Pistollato: Investigation, Writing - original draft, Writing - review & editing. Andrea Natale Tallarico: Writing - review & editing, Supervision. Susanna Reggiani:Conceptualization, Investigation, Formal analysis, Writing - original draft. Claudio Fiegna:Writing - review & editing, Supervision. Riccardo Depetro:
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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