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Impact of stress effect on triple material gate step-FinFET with DC and AC analysis

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Abstract

Step-FinFET is an improvisation in various electrical characteristics with a modified mechanism. The gate length 20 nm, 15 nm, 20 nm has allowed an acceptable driving current and considerable power consumption which longer the battery life. The study consist of electron density, electron velocity, mobility, electric field, and surface potential to relate the improved device performance. The major variation of drain current due to stress effect, tunneling, saturation factor, and minority factor has been investigated. This paper analyzes the parameters like transconductance (Gm), Drain conductance (gd), input capacitance (Cgg), cut off frequency (fT), power consumption, etc., for verifying the RF and analog application. Various short channel effect (SCE) also studied in terms of threshold voltage (Vth), sub-threshold swing (SS), drain induced barrier lowering (DIBL) and On/Off ratio are investigated with different gate length and drain bias. As a result the minimum values of threshold voltage, SS and DIBL calculated for gate length of 15 nm are 0.2426 V, 69 mV/dec, 14.6 mV/V, respectively.

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Acknowledgements

We would like to acknowledge National Institute of Technology Agartala and NIT Silchar for logistic support.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Tripura, 799046, India

    Rinku Rani Das, Atanu Chowdhury & Apurba Chakraborty

  2. Centre of Excellence for Green Energy and Sensor Systems, Indian Institute of Engineering Science and Technology, Shibpur, Howrah, 711103, India

    Santanu Maity

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  1. Rinku Rani Das
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  2. Atanu Chowdhury
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  4. Santanu Maity
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Correspondence to Santanu Maity.

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Das, R.R., Chowdhury, A., Chakraborty, A. et al. Impact of stress effect on triple material gate step-FinFET with DC and AC analysis. Microsyst Technol 26, 1813–1821 (2020). https://doi.org/10.1007/s00542-019-04727-2

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