PRO: A periodical reset optimized page migration scheme for hybrid memory system

Abstract

Due to its attractive characteristics, phase change memory (PCM) has emerged as a promising candidate to be used in main memory of embedded systems in the future. However, the write endurance problem has restricted its application in practical. Discussions regarding on hybrid memory page replacement mechanism have dominated research in recent years. Most existing schemes lack the detection for the locality regulations of memory access and do not take migration efficiency into consideration. In this paper, we rethink data access features and conduct further research on inter-reference distance to exploit the locality regulations of workloads in embedded systems. Then, propose a novel page migration scheme, Periodical Reset Optimized Page Migration Scheme (PRO), which is a hardware-software coordination algorithm. PRO largely reduces the number of write operations in PCM with limited swap operations. Meanwhile, it reduces the write operations by an average of 88.75% and decreases the average access time by an average 11.47% compared with the typical migration schemes.

Introduction

Industry and academic researchers have realized that modern applications exhibit increasing demand for large memory capacity to maintain the performance requirements in the embedded systems[1]. Main memory consisting entirely of DRAM has already hit the energy and scalability limits, which have motivated the search for alternatives to replace DRAM as main memory [2].Phase change memory (PCM) has been considered as a promising candidate for future main memory. PCM promises higher bit density and lower cost per bit than traditional DRAM. In addition, it demonstrates a comparable access speed to DRAM and is compatible to CMOS process technology[3]. Thus, researchers enable cost-effective hybrid main memory system with two partitions: DRAM and PCM, where PCM is slower but larger than DRAM. Combining PCM with a relatively small amount of DRAM can exploit the advantages of the high capacity of PCM and the low latencies of DRAM [3], [4], [5], [6].

Prior researches generally confirm that PCM can give benefits when utilized as an additional memory structure in hybrid memory hierarchy [6].Two hybrid memory topologies have been proposed in the literature as shown in Fig. 1. In flat memory, the processor can directly access DRAM and PCM. Data stored in PCM can be accessed via instructions and exchanged between DRAM and PCM straightforwardly [5].In hierarchical memory, processor should access PCM via DRAM.PCM is accessed only when DRAM miss occurs [1].

The hierarchical memory uses DRAM as an upper level cache of PCM main memory. The DRAM cache is hidden to the operating system which is similar to L1 or L2 cache.PCM is accessed only when the DRAM cache miss occurs. In the hierarchical memory architecture, the PCM main memory can still utilize an intact page replacement policy based on LRU algorithm or CLOCK algorithm [7], [8], [9], [10], [11], [12], [13], [14]. However, since the DRAM cache is transparent to the operating system, all actions related to the DRAM cache should be implemented by an extra hardware in the hierarchical memory architecture, thus deploying fully associate placement in hierarchical memory architecture is difficult. Moreover, the data consistency technique should be considered between DRAM cache and PCM main memory.

The flat memory organizes DRAM and PCM on the same layer and manages them together under a single physical address space with no additional hardware cost. In addition, in the flat memory, fully associate placement is possible and the DRAM and PCM space could be used more effectively. Because of the advantages mentioned above, this work focuses on the flat memory.

However, like flash memory, the physical properties of PCM dictate it suffering problems on write operations. Table 1 shows the physical properties of DRAM and PCM [8]. Generally, the latency and energy consumption of write operations in PCM are larger than that of DRAM [4]. Furthermore, PCM is suffering from the endurance problem that each cell can only be written ${10}^6-{10}^8$ approximately, which has a higher probability to be worn out in the limited write times. These limitations may significantly impact system performance, such as shorting the lifetime of memory system, restricting the usefulness of PCM in commercial system. Therefore, the write traffic to these PCM devices must be reduced.

To mitigate the endurance problem in hybrid memory system, discussions regarding on hybrid memory page replacement mechanism, which aim to avoid excessive write operations in PCM, have dominated research in recent years [7], [8], [9], [10], [11], [12], [13], [14].

In this paper, we restudy the data access features in the applications and conduct further research on inter-reference distance to exploit the locality regulations of workloads. According to the research, we find that employing inter-reference distance in the design of memory controller can be a better way to pick the hot write pages out. Only employing a global request counter to represent inter-reference distance information to dynamically predict the locality of actively access pages for the whole blocks instead of setting the write counter for each unit of the memory is the highlight of this paper. As shown in the simulation results in this paper, the PCM write count of PRO is significantly decreased than the other algorithms for most cases. For our design, the inter-reference distance information can be represented by the number of accesses that hybrid memory receives approximately, which can be implemented by a global request counter. Such simple design greatly reduces the complexity of memory controller. Then, an efficient page migration scheme for hybrid memory, Periodical Reset Optimized Page Migration Scheme (PRO), is proposed, which could pick the hot write pages out and reduce the number of writes in PCM with limited swap operations. The main contributions of this paper are summarized as follows:

1) We find that employing inter-reference distance in the design of memory controller can be a better and simple way to pick the hot write pages out.

2) We propose an efficient page replacement mechanism for hybrid memory system, which could reduce the number of writes in PCM with limited swap operations.

PRO reduces the write operations by an average of 88.75% compared with the state of art. At the same time, it improves the efficiency of each migration and reduces average memory access time effectively.

The remainder of the paper is organized as follows. Section 2 introduces the related work and research motivation briefly. Section 3 presents the analysis of inter-reference distance in workloads. Section 4 describes the details of PRO. Section 5 provides the experimental setup and results with discussion on performance. Finally, we conclude this paper in Section 6.