Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter

Abstract

This manuscript reports the back-gate effects on device-level performance of a heterojunction TFET on SELBOX substrate (HJ-STFET). The proposed structure implements a stacked gate oxide where the conventional SiO₂ is replaced by a SiO₂/HfO₂ in a stacked manner to increase its On-current. A back gate (BG) is also considered in the proposed TFET to enhance the device-level performance. Investigation of DC, RF and linearity parameters such as drain current, transconductance, electric field, parasitic capacitance, cut-off frequency (f_T), gain bandwidth product (GBP), intrinsic delay (ꞇ), higher-order of g_m (g_m2, g_m3), VIP2, VIP3, IIP3, IMD3, and 1-dB compression point are carried out for the proposed TFET and the results are compared with other conventional structures. Performance evaluation shows that BG-HJ-STFET is a suitable candidate for distortionless and high-frequency applications. In addition, analysis of DC and transient behaviour of a CMOS TFET inverter using the BG-HJ-STFET is thoroughly investigated to verify its circuit-level performance.

Introduction

Although scaling is adopted to meet technical requirements, there are several issues in MOSFETs that need to be addressed as device dimensions have reduced over time [[1], [2], [3], [4]]. The inability of MOSFETs to withstand downscaling has led the researchers and research groups to look out for novel devices which may be considered as alternatives to MOSFETs such as carbon nanotube FET [5], graphene FET [6], tunnel FinFETs [7], TFETs [8], nanowires FETs [9], and negative gate capacitance FETs [10]. Out of these devices, we emphasize on TFETs as an alternate for MOSFETs in this manuscript. Tunnel Field Effect Transistors (TFETs) are gated reverse-biased p-i-n diodes that can achieve sub-60 mV/dec subthreshold swing (SS) by the principle of the band to band tunneling [[11], [12], [13]] which in turn make them turn on at a low operating voltage [8]. TFETs also exhibit low Off-state current due to their mechanism of carrier transport based on band to band tunneling (BTBT) [12]. There are different techniques to have better DC performance in TFETs. It can be done through modulating the tunnel barrier by changing the gate voltage and using the density of states (DOS) switching. Using III-V compound semiconductors with a direct bandgap also helps to achieve higher On-currents [14]. In addition, TFETs need a highly abrupt doping concentration to have a steep barrier [15]. The presence of interface traps is another concern while achieving steep energy band edges for effective DOS switching [16]. Since heterojunction TFETs achieve low tunneling length with the comparatively lower electric field the presence of interface traps could be negated [17]. Short channel effects are minimized effectively because of the dependency of the total current on the tunneling current concentrated at the tunnel junction. Another advantage of TFETs is its compatibility with CMOS fabrication techniques. However, TFETs do suffer from issues like lower On-current and ambipolar conduction. High-k gate dielectric in a vertical stack manner is adopted to increase overall electric field which in turn increases On-current [18] whereas to reduce ambipolar conduction current asymmetric doping at source and drain is adopted [18]. Keeping in view of the above, this article presents a Ge/Si heterojunction based TFET with vertical gate stacked to increase On-current which in turn increases overall DC performance. Gate oxide stack is made considering SiO₂/HfO₂ in a vertical manner. In addition, a narrow gap is created in the buried oxide (BOX), through which the channel region gets connected to the bulk region below the BOX of the SOI substrate. This gap allows heat flow from the channel to bulk region to prevent the device from thermal breakdown occurs due to impact ionization [19]. The SELBOX structure also reduces the leakage current by trapping some electrons through the gap which is difficult to pull for the low drain field under subthreshold regime of operation [20]. In addition, a back gate is considered in the proposed structure that influences the overall performance of the device by enhancing the gate controllability on the channel region [21]. In this regard, a comparison study has been made between the TFETs with and without back gate. A device-level comparison study has also been carried out by considering TFETs on SELBOX substrate without having any heterojunction i.e. monojunction with the TFETs on SELBOX substrate with heterojunction. Finally, the circuit-level performance is analyzed for the back gated Ge/Si TFET with SELBOX (BG-HJ-STFET) by taking a digital inverter circuit.