Research paperCompact Si JFET model for cryogenic temperature
Introduction
Junction Field Effect Transistors (JFETs) due to high input resistance and amplification factor, low intrinsic noise and compatibility with Bi-CMOS/Bi-CMOS-DMOS technologies are widely used in input and subsequent cascades of low-noise operational amplifiers, comparators, secondary power sources, stabilizers and other analog circuits of low-temperature electronics [1], [2]. In Fig. 1a and b the typical structures of the integrated [3] and discrete [4] JFET transistors are shown.
Different versions of compact models of JFETs were developed previously and built into the SPICE-like software tools for electronic circuits simulation [5], [6], [7], [8], [9], [10], [11]. These models guarantee the satisfactory accuracy only in the standard temperature range from 213 K to 423 K (−60 °C to +150 °C).
In fact, there are no publications on the simulation of static I-V characteristics in the low temperature range. Few attempts were made to use the conventional JFET models for the qualitative analysis of analog circuits characteristics in the low-signal mode [12], [13], [14]. In our previous work [15] we tried to use the improved version of Shichman–Hodges model for analog circuit simulation in cryogenic temperature range, but the possibilities of this model were limited.
Unfortunately, no models are applicable to IC simulation at the cryogenic temperatures.
Therefore, the goals of this work are:
- (1)
To overcome the limitations of the conventional JFET models and develop the adequate compact Si JFET model with extended temperature range from 373 K down to 73 K;
- (2)
To include the developed Low-T JFET model into commercial versions of SPICE-like software tools to expand them to electronic circuit simulation for cryogenic applications.
Section snippets
Model formulation
The most advanced in practical IC simulation is the standard JFET model Level 3 (Statz model [8]) implemented in popular SPICE-like simulators HSPICE, LTSpice, Eldo and others. It was employed as a core for the Low-T model version development. It assumes the common smooth I-V equation that describes JFET static I-V characteristics in three regions of operation: pinch-off, saturation and linear:where IDS is the drain to source
Measurement of I-V-characteristics at cryogenic temperature
The measurement at cryogenic temperature was done with the setup at Minsk Research Instrument Making Institute [19]. In the core of the setup is a chamber with a DUT (device under test) (see Fig. 6). The sample was mounted on a tall steel bar that was immersed into a Dewar with liquid nitrogen with temperature around 77 K. The bar inside the barrel was moved up and down to adjust the temperature. The transistor’s temperature was monitored using a copper-copel (type M) thermocouple. The external
Si JFET model parameters extraction in the cryogenic temperature range
To determine the set of parameters for the proposed JFET SPICE model in the extended temperature range, we have developed an automated hardware-software subsystem that performs the following tasks [18]:
- 1.
Measurement of the standard set of I-V and C-V characteristics for JFET at different values of temperature { Ti }.
- 2.
Determination of the complete set of JFET model parameters (level = 3) based on experimental measurement data obtained at room temperature. The method of parameter identification uses
Conclusion
The Low-T version of the JFET standard SPICE model Level 3 was developed for circuit simulation in the extended low temperature range down to 73 K (−200 °C). The model is universal and applicable to different types of JFET structures with regular and irregular output I-V curves. It takes into account the effects of cryogenic temperatures: increase in saturation voltage VDsat, pinch-off current Ip, decrease of transconductance BETA, negative slope of output I-V characteristics, and increase of
CRediT authorship contribution statement
Konstantin O. Petrosyants: Conceptualization, Project administration, Writing - review & editing. Mamed R. Ismail-zade: Methodology, Investigation, Writing - original draft. Lev M. Sambursky: Methodology, Validation, Writing - review & editing.
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgements
This work was implemented in the framework of the Basic Research Program of the National Research University Higher School of Economics (HSE) No TZ-99, Russian Foundation for Basic Research (grant 18-07-00898 A), and by RFBR and NSFC according to the research project 20-57-53004.
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