A BIMOS-based 2T1C analogue spiking neuron circuit integrated in 28 nm FD-SOI technology for neuromorphic application

Abstract

Neuromorphic computing is an emerging field of investigation for new algorithm solutions and daily life applications. We propose a novel approach to achieve an operator which uses a parasitic bipolar metal oxide semiconductor filed effect transistor combined with a capacitor and a n-type metal oxide semiconductor filed effect transistor. The resulting BIMOS-based leaky-integrate-and-fire spiking neuron circuit is integrated on thin silicon film in 28 nm high-k/metal-gate advanced complementary metal oxide semiconductor technology. The proof of concept is brought by 3-dimensional technology computer-aided design numerical simulations, and then validated by electrical characterization of the two-transistors-one-capacitor demonstrator. The underlying physical phenomena involved in the spiking mechanism are identified, explained and modelled. Low power consumption is obtained. In addition, the spiking neuron device benefits from intrinsic electro-static discharge robustness.

Introduction

Since the Moore’s law is close to its end [1], microelectronic industry is looking for new paradigm to pursue technological improvements that have shaped our information society. Beside quantum computing, neuromorphic engineering is one of the most promising tracks. Mimicking biological nervous systems at the integrated circuit level, very large scale integrated neural processors [2] are much more energetically efficient to perform neuromorphic computing than standard architecture based on Von Neuman finite state machine [3]. In such systems, a huge number of neurons has to be integrated and interconnected on a silicon die in order to build the artificial neural network (ANN). The neuron circuit design is one of the fundamental building blocks of the system. Its area and energy consumption are of primary concern. Even though formal neurons can be used for perceptron architecture [4], [5], [6], the spiking neuron (SN), which allow time-encoding, are preferentially used in state-of-the-art developments. Several types of SN circuit design have been already proposed in the literature [7], [8], [9], [10], [11], [12], [13], [14].

Fig. 1a shows one of the state-of-the-art SN design [12] that uses very few components (6 transistors and 2 capacitors). Typically, the synaptic current I_SYN charges C_m whose drop voltage is sensed by the MP₁/MN1 inverter. When it switches, C_m is alternately charged even more and discharged by MP_Na and MN_K to shape a voltage spike across it. The charge/discharge alternation is allowed by the MP₂/MN₂ inverter delay. The capacitor C_K provides a refractory period. To reach the reported 4 fJ/spike consumption, the C_m and V_DD supply are reduced to 4 fF and 200 mV respectively, leading to a 100 mV spike swing. This very high energy efficiency is at the cost of variability increase due to the deep subthreshold operation of the transistors under a 200 mV supply voltage. Typical V_MEM and I_SYN chronograms of a class 1 excitable SN [15] are also presented on Fig. 1b. This type of neuron provides tonic spikes at a frequency proportional to the excitation current.

One of the main parameters to be taken into consideration is the time-encoding speed directly related to the time-constant of the SN design. It is governed by the circuit resistances, capacitances and current drives. These values directly impact both energy and area consumption. In real-time real-life signal processing, the human range time constant (ms range) is relevant. It minimizes the energy consumption through the average spiking frequency lowering. However, the area consumption is maximized because higher capacitance values have to be integrated. Conversely, in a batch data processing context, decreasing the time constant is relevant to accelerate the computing. It reduces the area penalty at the expense of the energy consumption. A trade-off has to be found, depending on the target application.

This paper presents deeply the two-transistors-one-capacitor (2T1C) SN circuit introduced for the first time in [16] and based on the use of fully depleted silicon on insulator (FD-SOI) parasitic bipolar metal oxide semiconductor filed effect transistor (BIMOS). The proposed BIMOS-based (BB) leaky-integrate-and-fire (LIF) SN circuit allows area and energy consumption reduction and can be used in both real-time real-life signal and batch processing contexts by tuning the capacitor value. The paper is organised as follow. In Section 2, the BB LIF SN circuit is depicted in detail. In particular, the implemented SN model is exposed, as well as the circuit schematic and its operation mechanisms. Then 3-dimensional technology computer-aided design (3D TCAD) numerical simulation results are shown in Section 3 to illustrates the BB-LIF SN operation. Next, in Section 4, measurements performed on a partially integrated demonstrator are compared with simulated results. Thereafter, a compact model of the FD-SOI BIMOS is proposed and SPICE simulation results of the BB LIF SN transient behaviour are presented in Section 5. Section 6 is dedicated to a 3D TCAD study of a fully integrated BB LIF SN circuit design. And finally, the electro-static discharge (ESD) robustness of the proposed design is assessed in Section 7.