Efficient FPGA implementation of corrected reversible contrast mapping algorithm for video watermarking

Abstract

This paper analyses and rectifies the shortcomings of reversible contrast mapping (RCM) algorithm for invisible watermarking. The proposed corrected RCM algorithm is tested by taking a gray scaled video input. The quality of services and structural similarity index matrix (SSIM) of each frame of the input video are tested in software environment. The video is obtained by OV7670 camera through Zed-board in fully field programmable gate array (FPGA) based hardware environment. FPGA devices based corrected high level synthesis of the proposed algorithm is presented. The suggested system engages pipeline structure and practices parallelism to achieve high performance. The quality of services and SSIM are also tested using FPGA devices and the comparative results with software implementations are explained. To process thirty (640 × 480) image blocks with 150 MHz clock we obtain a latency of 876.626 ns with throughput 62.328 Mbps. The critical path for single cycle is 5.992 ns. The number of resources essential is similar for watermark decoding with an improved schedule. The results acquired after implementation on Xilinx Virtex 7-XC7V2000T and programmable system-on-chip (Zynq - XC7Z030) FPGA devices confirm the practicability of real-time use with low cost and great speed.

Introduction

Nowadays to stay away from unproven use of digital multimedia information and to verify the genuineness, digital watermarking is mostly used [1,2]. Digital watermarking can be classified depending on the types of input informations being used like image, text, video watermarking etc. It can further be classified based on the basic characteristics and properties of the applications like robustness, data payload, fidelity and other limitations [3]. The patterns of bits or digital informations like digital signature, finger print that are embedded into the original or input multimedia data are called watermarks. If the watermark is visible after embedding it is called visible watermarking otherwise it is known as invisible watermarking [4,5]. VLSI implementations for both invisible and visible digital watermarking using complementary metal oxide semiconductor (CMOS) technology had been proposed [6], [7], [8]. Later a still digital camera is used to present the VLSI implementation of visible watermarking using 0.35 μm based CMOS technology [9]. To reduce space required for hardware implementation, the discrete cosine transform (DCT) with dual frequencies and voltages had been taken into consideration to present VLSI architecture for both visible and invisible image watermarking [10], [11], [12]. Digital watermarking is not a lossless data embedding method. It is used when extraction of the watermark is not required by third party or the receiver. To recover back the multimedia data without any loss, the third party requires the watermark or some additional information. In some digital watermarking algorithms, without having any additional information the watermark may be extracted back but it causes harm to the cover data. Clearly some information about the cover data is lost during data extraction. Moreover for some applications like medical imaging and military data, small imperceptible distortion due to watermarking process is not acceptable. To overcome the drawbacks of digital watermarking, reversible watermarking (RW) algorithm is used to eliminate the alteration and recover both the data and the watermark [13], [14], [15], [16], [17], [18], [19], [20]. Recently RW has become popular in tele-surgery, remote based patient monitoring and military domain. RW provides high imperceptibility and secured communication in image processing based applications. There are many different types of methods used for RW algorithms [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37]. Some popular methods of RW are difference expansion (DE) [15,[17], [18], [19],33,34], histogram bin shifting [35], [36], [37], RCM [13,14,16] and prediction error expansion (PEE) [22,29,30,32]. The histogram bin shifting and its modified version are used to increase the authenticity but they suffer from low embedding capacity. To improve the overall performance of RW, PEE is most acceptable choice but it suffers from large payload size to embed prediction error information which increases distortion. Both DE and RCM are spatial domain type algorithms where a linear transformation is used to realize the reversibility. In DE algorithm, the linear transformation is applied only on the pixel intensity values that cause the need of location map control mechanism. In other hands to reduce the arithmetic complexity, the linear transformation in RCM algorithm is applied on pixel intensity values as well as the pair of pixel locations. In this way under a low mathematical complexity RCM provides higher embedding bit rate than DE in single iteration. That makes the RCM most attractive algorithm for RW particularly for real-time implementation.

RCM method [14] for video watermarking is utilized in this work. Based on the mathematical analysis, it is found that there are shortcomings in the embedding algorithm. The invertible property of the algorithm is not satisfied at all cases followed by different conditions that are explained in section 3. After correcting the shortcomings we have provided the rectified algorithm. Very low mathematical complexity along with high data embedding can make the method most consequent use in research. The basic concept of RCM algorithm is discussed in other studies [13], [14], [15], [16]. In this paper, we have focused to explore and implement high speed VLSI architecture by following the reward of RCM based watermarking technique by taking a video input signal. Foremost attention is given on developing a less hardware resources based architecture. For this purpose, hardware implementations of digital watermarking for different types of multimedia data are considered [38], [39], [40], [41], [42], [43], [44], [45], [46], [47], [48], [49], [50].

Literature witnesses FPGA based hardware implementations for RCM method [41,42,48]. A 6 stage pipeline is required for VLSI architecture of RW [41]. It requires high numbers of resources which reduces the speed. A modified RCM method [42] is proposed by increasing the contrast value to 5 from 3. The embedding capacity will reduce drastically for these modifications due to larger bit stream of location map. Also to embed the larger bit stream, more numbers of pipeline cycles are required. In the proposed work the same steps are followed for corrected RCM method based video RW and in addition to reduce number of pipeline cycles and hardware resources, the high level synthesis approach based controller design [49] is used. In our previous work [49], the high level synthesis (HLS) approach is proposed for DE based RW. This work uses the HLS approach to present the controller followed by suitable pipeline structure and practices parallelism for corrected RCM method.

The corrected architecture has been presented and verified using VIVADO HLS tool. The key objective of the present work is to reduce the complexity without harming the performance. Video processing using FPGA is always challenging and complicated. To overcome the complexity and provide a simple way for VLSI implementation of image processing algorithms on FPGA environment, the VIVADO based HLS tool is most preferred choice to process a continuous signal like video [51,52]. The RCM method is implemented using VHDL and synthesized into FPGA environment. The video is obtained by OV7670 camera through Zed-Board in Zynq system-on-chip (SoC) platform.