Abstract
This paper presented a fully depleted silicon on insulator (FD-SOI) MOSFET in nano scale size with deployment the quasi two dimensional β-Ga2O3 material to improvement electrical properties. The main idea of the proposed structure is embedding a layer of the β-Ga2O3 in the drain region. Due to the β-Ga2O3 material features, the electric field distribution near the drain and gate side will be change and peak of the electric field of the proposed structure is diminish. The embedded layer of the β-Ga2O3 material in our work has an important effects on the electrical and thermal characteristics. In this paper, characteristics of the proposed structure is compared with the prevalent SOI and improvement of characteristics in our work are shown. The features such as the electric field, the potential distribution, the sub-threshold slope, the kink effect, the self-heating effect, punch through effect and DIBL effect are investigated and compared with prevalent SOI.
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Beta-gallium oxide (β-Ga2O3) is an emerging ultra-wide band gap semiconductor material for high-power device application because of the superior electrical properties of Ga2O3 such as a wide band gap (∼4.8 eV) and high breakdown field (∼8 MV cm−1).1–5 In addition, the β-Ga2O3 can easily be doped by n-type semiconductor and has a reasonably high electron mobility of ∼150 cm2 V−1 s−1 at room temperature.6 It also has potential for low power and low loss during high frequency switching in GHz regime.7 Ga2O3 has a high electron saturation velocity (υsat).8 Owing to its large band gap, the β-Ga2O3 is also predicted to be a good candidate for high temperature applications in electronics.9
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been used in many applications and there was a high interest among the researchers to study their electrical performances.10 By reduction of the gate length in nano scale size, short channel effects will be appear. SOI technology is a good way to improve the electrical performance with adding a buried oxide (BOX) layer between the active region of device and substrate.11 Effects such as parasitic capacitances, latch-up, sub-threshold slope and short channel effects will be improve in SOI MOSFET and it is a good candidate in vary applications at nano scale size.10 Despite that SOI technology has a good properties, but we are witness to vital problem such as the self-heating and the kink effect.12–14
In this paper we presented a new SOI MOSFET structure with a layer of the β-Ga2O3 in the drain region. In our work, we emphasis on the short channel effects. By inserting the layer of β-Ga2O3 (LβG-SOI MOSFET), the electric field in the critical region around gate and the drain side will reduce and we have better electrical performance vs a prevalent SOI MOSFET (P-SOI MOSFET).
Proposed Structure and Simulation Method
A 3D view of a prevalent SOI structure and the proposed structure are shown in Figs. 1a and 1b, respectively that we used a the β-Ga2O3 layer to amend the electric field at the proposed structure, which is located under the drain region. Both the structures are investigated at 20 nm technology and the thickness of silicon is 10 nm on the SOI technology. Important parameters of simulations in both the structures can be seen in Table I. For simulating both the structures, SILVACO-TCAD15 software is used. For achieving good physical results of the structures, some models such as SRH, Analytic, Incomplete Ionization, Fldmob, BBT, CVT, and Impact Ionization are used in the Silvaco TCAD. Auger recombination model and band gap narrowing (BGN) model are used to investigate the effects of the high carrier concentration. In thin channel thickness, due to confinement of carriers in the vertical orientation, quantum effects are used by applying a density gradient model. For checking temperature properties, lat.temp model and hcte.el model are considered in both the structures.14 All simulations are under same situation and at 300 Kelvin temperature. In this paper we worked on 〈100〉 direction with the 12 W mK−1 thermal conductivity at room temperature. Because of high interface charge and defect trap density between Si and Ga2O3, ionized impurity scattering (Coulomb scattering) causes to low mobility in the channel. Also there is a surface roughness scattering in the surface of device. All model are considered in ATLAS for achieving above effects of interface in structures. Interface charge density is considered at 5 × 1011 cm−2. For temperature simulation, a thermal contact considered at the substrates of both the devices. Work function of the gate electrode is considered 4.5 eV. In this work, for achieving the low and positive threshold voltage, the work function of gate has been chosen in an optimum range. We simulate both the structures with Victory Device simulator in the Silvaco TCAD for achieving correct results. Device simulator helps users to understand the physical processes in a device and to make reliable predictions of the behavior of the next device generation.15 Two and three dimensional modeling and simulation processes help users obtain a better understanding of the properties and behavior of new and current devices and helps provide improved reliability and scalability, while also helping to increase development speed and reduce risks and uncertainties.15 Note that to validate the accuracy of materials models, the simulation is calibrated by experimental data16 and the output characteristic of SOI MOSFET shown in Fig. 2.
Figure 1. Cross section view of (a) P-SOI MOSFET (b) LβG-SOI MOSFET structures.
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Standard image High-resolution imageTable I. Important parameters of simulation in both structures in this paper.
| Parameters | Value |
|---|---|
| Gate length, LC | 20 nm |
| Source/Drain region length, (LS, LD) | 20 nm |
| LSUB, Substrate length | 60 nm |
| Channel, Source, and Drain thicknesses, TA | 10 nm |
| BOX thickness, TB | 10 nm |
| Substrate thickness, TS | 60 nm |
| Gate oxide thickness, TO | 5 nm |
| Doping concentration of Channel region, NA | 3 × 1018 cm−3 |
| Doping concentration of Source region, ND | 1 × 1020 cm−3 |
| Doping concentration of Drain region, ND | 1 × 1020 cm−3 |
| Doping Substrate | 3 × 1017 cm−3 |
| Doping concentration of N in layer of β-Ga2O3 | 5 × 1017 cm−3 |
| β-Ga2O3 Layer length, LP | 10 nm |
| β-Ga2O3 Layer thickness, TP | 9 nm |
Figure 2. Simulation of output characteristics calibrated by experimental results.16
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Standard image High-resolution imageResults and Discussion
As mentioned before, the LβG-SOI MOSFET structure comprises a layer of the β-Ga2O3 in the drain region and main idea of this change in the proposed structure, is amending the electric field in the critical region near of the drain and the gate. To see the effect of the added layer, we demonstrate the electric field in Fig. 3. As we see, the lateral electric field in both the structures along "A–B" cut-line, located 0.1 nm from the surface of structures are shown. Regarding to Fig. 3, we have lower the electric field in the proposed structure. Due to inserting the β-Ga2O3 layer and because of high breakdown field of the β-Ga2O3 material, at higher drain voltage, the electric field in the LβG-SOI MOSFET has a lower peak vs the P-SOI MOSFET. Lower the electric field peak tends to lower velocity of electrons and holes for trapping in the oxide of the gate and hot carrier effect will be diminish and will be obtain better reliability vs the P-SOI MOSFET.
Figure 3. Electric field distributions of P-SOI MOSFET and LβG-SOI MOSFET structures by cut-line at A-B.
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Standard image High-resolution imageThe lattice temperature increment is an important problem in degrading the electrical efficiency of the structures. In Fig. 4, we demonstrate the lattice temperature in the lateral position along throughout of device. As described, by decreasing the electric field in the proposed structure due to inserting a layer of the β-Ga2O3 material, we can see a lower maximum the lattice temperature in the LβG-SOI MOSFET vs the P-SOI MOSFET. Figure 4 clearly shows improvement of the lattice temperature in the proposed structure in comparison with the prevalent SOI and reliability of the proposed structure that is the most important parameter of device will improve and the LβG-SOI MOSFET can be used at higher drain voltages.
Figure 4. Lattice temperatures of P-SOI MOSFET and LβG-SOI MOSFET structures by cut-line at A-B.
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Standard image High-resolution imageAs we described, by decreasing the lattice temperature in the proposed structure, we obtain a lower the electron scattering and due to this effect, the higher electron mobility in the proposed structure will be achieve. In Fig. 5, the electron mobility of both the structures along the "A–B" cut-line in the channel position, located 0.1 nm from the surface of the structures is shown. By increasing the drain voltage and at the higher electric field, the lattice temperature goes up and carrier scattering increases and as we described, at this conditions, the electron mobility tends to reduction. The lower temperature in the proposed structure is a reason to get higher effective the electron mobility in comparison with the P-SOI MOSFET. According to Eq. 117:
In Eq. 1, μeff, 0 represents the effective mobility at room temperature, T is the average of temperature in the channel, T0 is the room temperature, and k is the temperature dependence of mobility in semiconductor. As we mentioned and by above equation, by decreasing the lattice temperature in the proposed structure, we will obtained higher effective mobility of the electron and as a result, we can see improvement in reliability of the structure vs the P-SOI MOSFET.
Figure 5. Effective electron mobility of both structures in channel position.
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Standard image High-resolution imageBy inserting an insulation layer under the active region in SOI technology, with increasing drain voltage, generated heat cannot be dissipate from device and temperature in the critical region of structure goes up. One of the important problems in SOI technology is the self-heating effect and at the shorter dimensions of channels, this effect will be more important. At Fig. 6, we show the self-heating effect of both the structures and we can see improvement of the proposed structure. By inserting layer of the β-Ga2O3 and as we mentioned, due to higher breakdown field of β-Ga2O3, by increasing drain voltage, the lattice temperature in the proposed structure is less than the prevalent SOI and we have better condition respected to the P-SOI MOSFET and it is clearly shown in Fig. 6.
Figure 6. Lattice temperature vs drain voltage for P-SOI MOSFET and LβG-SOI MOSFET structures.
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Standard image High-resolution imageIn Fig. 7 we show the sub-threshold slope of both the devices in different channel lengths. As we see in the figure, the proposed structure has a lower sub-threshold slope than the P-SOI MOSFET. Due to Eq. 2, because of lower temperature in the proposed structure that we described in last sections, improvement of sub-threshold slope in the LβG-SOI MOSFET clearly shown in the figure. The ideal value for SS is about 60 (mV decade−1) which occurs at 300 K and for the other temperatures, sub-threshold slope can be calculate as18:
As the LβG-SOI MOSFET structure has lower lattice temperature than P-SOI MOSFET, the sub-threshold slope of the proposed structure will have a less rates in the different channel length sizes and improvement of the proposed structure compared to the P-SOI MOSFET can be seen in the Fig. 7.
Figure 7. Sub-threshold slop of P-SOI MOSFET and LβG-SOI MOSFET structures.
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Standard image High-resolution imageBy increasing the drain voltage, when the electric field reaches a critical value, the electrons and holes can get high kinetic energy and due to the impact ionization, electron and hole pairs will be generate. At higher electrical field, probability of the impact ionization phenomenon increases and because of lower the electric field in the proposed structure, lower the electron and the hole will create and this probability will decrease. To better understanding of this phenomenon, we demonstrate the logarithm of hole concentration of both the structures in Fig. 8 along the "C-D" cut-line, located 9 nm from the surface of structures. As shown in the figure, the logarithm of hole concentration in the proposed structure is lower than the P-SOI MOSFET. We know that because of the BOX layer, the generated holes due to the impact ionization has no path to go to the negative potential side, and holes will accumulated at the channel region inside the source side and it will effects on the drain current and also reliability of the structure reduces. By decreasing the accumulated hole, one of the most important problems of SOI technology that we called the kink effect, improves and we have lower power consumption. In Fig. 9, we illustrate the drain current vs the drain voltage characteristics of both the structures. As we see in the figure, in the P-SOI MOSFET structure, the kink effect is happens at the lower drain voltage and as we mentioned, by decreasing the hole concentration in the proposed structure, the kink effect improvement in our structure is shown in the figure.
Figure 8. Hole concentration distribution of P-SOI MOSFET and LβG-SOI MOSFET structures by cut-line at C-D.
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Figure 9. The kink effect in the output characteristics of both the structures.
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Standard image High-resolution imageIn the weak inversion condition, by increasing the drain voltage and at higher the electric field, the potential barrier between the channel region and the source region will be change. This effect at shorter gate lengths, will be clearer and sooner happens. At the higher drain voltages and due to effect of the electric field, when the barrier height inside the channel carriers at near of the source side is decreased, the DIBL effect happens. DIBL (Drain Induced Barrier Lowering) effect is one of the short channel effects. The electrons from the source side will flow to the channel region and effects on the drain current. At this condition, the carriers in the channel region is not only controlled by electrode of the gate and even the drain voltage is involved in this matter too and reliability of device decreases. In Fig. 10 we illustrated the potential barrier in lateral position at throughout of device. As we see in the figure, the potential barrier in lateral position of both the structures at Vdrain = 0.1 V and Vdrain = 1 V is shown. By increasing drain voltage, the potential barrier for both the structures will reduce, but we have less reduction in the proposed structure vs the P-SOI MOSFET structure. On the other hand, for better understanding the DIBL effect, we illustrate the conduction band diagrams of both the devices in Fig. 11. As we see in the figure, and as we said, by increasing drain voltage, higher barrier of potential of the proposed structure is shown and one the important parameter in short channel effects in the LβG-SOI MOSFET structure, clearly improves.
Figure 10. Drain induced barrier lowering of both the structures in different channel lengths.
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Figure 11. Conduction band of energy in both the structures by cut-line at A-B.
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Standard image High-resolution imageWe can see in Fig. 11, at the higher drain voltages in the positive side, reverse bias p-n junction increases. In the proposed structure, due to embedding the layer of β-Ga2O3 material we are witness to amending the electric field and the potential distribution, and the depletion region and p-n junction increment at the drain side, is less than the P-SOI MOSFET and as a result, another effect that is called the punch through effect is improved. Punch through effect is another effect of the short channel effects. In the short channel lengths and at higher drain voltage, the depletion region of the source and the drain region gets close to each other and the punch through effect happens. For better understanding of this phenomenon, we show the potential distribution contours of the P-SOI MOSFET and the LβG-SOI MOSFET in Figs. 12a and 12b, respectively. As we described and as we see in Fig. 12, the depletion region in the drain side improves and probability of the punch through effect will be less than the P-SOI MOSFET.
Figure 12. Potential contour distribution lines of (a) P-SOI MOSFET (b) LβG-SOI MOSFET.
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Conclusions
In this paper we present a SOI MOSFET with a layer Ga2O3 to amending the electric field and we demonstrate better electrical performance in comparison with a prevalent SOI MOSFET. Improvement of the electric field, the potential distribution, the self-heating effect, the kink effect is shown in this paper. By amending the potential distribution in the proposed structure, we demonstrate improvement of DIBL effect and the punch through effect. Results of the proposed structure demonstrate a good structure which can be used for high voltage application and low power performances.