On the improved performance of thermoelectric generators with low dimensional polysilicon-germanium thermocouples by BiCMOS process

Highlights

• This paper proposes to develop TEG chip by BiCMOS process, where silicon and germanium materials have been shown to achieve higher energy harvesting performance. The BiCMOS process in foundry services available to semiconductor industry is shown to be a perfect platform for TEG designs.

• In state-of-the-art BiCMOS process, the base thickness (EPOLY layer) from 20 to 150 nm has been shown to have higher thermoelectric figure-of-merit. This change of thermoelectric property shall affect the calculation of thermocouple dimension for optimal TEG performance. With the progress of BiCMOS in deep sub-micron ranges such as 3 nm process, higher TEG performance is around the corner.

• The thermocouple length shall match the thermal/electrical resistance thereby maximizing the power factor and voltage factor. By 0.35 μm 3P3M SiGe BiCMOS process, the optimal thermocouple dimension is 50 × 2 × 0.350 μm for p- and 50 × 2 × 0.280 μm for n-type thermolegs. By 0.18 μm SiGe 3P6M BiCMOS process, the thermocouple dimension is 45 × 2 × 0.380 μm for p- and 45 × 2 × 0.200 μm for n-type thermolegs. The power factors are respectively 0.242 and 0.125 μW/cm2K2, and the voltage factors are 10.04 and 25.91 V/cm2K in simulation. A 1.2 mm × 1.2 mm TEG chip has been developed by the BiCMOS process. Experimental verifications of the TEG performance are shown to match the numerical simulations, and the performance are superior to all in the open literature. TEG chip designs and implementation by BiCMOS process in semiconductor foundry may be the solution to engineering applications of TEGs in human body temperature range.

Abstract

Standard complementary-metal-oxide semi-conductor (CMOS) process for the advantages in batch production, low cost, and mostly importantly, scalability has been applied to thermoelectric generator (TEG) designs, where silicon materials are preferable for monolithic circuit integration. In this work, the BiCMOS process is found to be a perfect platform for TEG designs to achieve higher performance by the polysilicon-germanium thin film layer. Simulations of the TEG designs by 0.35 μm SiGe 3P3M and 0.18 μm SiGe 3P6M BiCMOS processes (TSMC) show that the power factors are respectively 0.242 and 0.125 μW/cm² K², and the voltage factors are 10.04 and 25.91 V/cm² K. Both are shown to be superior to all micro TEGs by semiconductor process in the open literature. Experimental verifications confirm the simulation results and validate the effectiveness of TEG designs by the polysilicon-germanium thin film layer in BiCMOS process.

Introduction

The advent of semiconductor foundry more than 3 decades ago has facilitated the progress of fabless IC companies to spearhead many innovations in micro-sensor industry. In energy harvesting studies, Strasser et al. [1] first proposed the TEG design by using polysilicon and polysilicon-germanium thermoelectric layers so as to be compatible with CMOS process. Standard complementary metal-oxide-semiconductor (CMOS) process has since been applied to thermoelectric generator (TEG) development. With acceptable Seebeck effect found in doped polysilicon layers, many recent TEG designs have adopted the CMOS process [2,3], where the polysilicon deposition facilitates high integration density of thermocouples on a wafer [4]. A TEG design was developed by standard CMOS process using foundry service a decade ago [5]. Another TEG design by CMOS process has also been proposed to increase the thermocouple area density, and hence the harvesting performance [6]. In Micro-Electro-Mechanical Systems (MEMS) related works, a 1 cm × 1 cm TEG design with aluminum and polysilicon layers was proposed to have open-circuit voltage 0.746 V and output power 0.363 μW by simulation [7]. Xie et al. [8] also applied similar MEMS process to a 1 cm × 1 cm TEG delivering 16.7 V open-circuit voltage and 1.3 μW output power under forced convection. Engineering applications of the above TEG designs, however, have been limited by their poor performance. Major improvements in thermoelectric materials selection and in CMOS-compatible process are necessary.

In addition to semiconductor technology, other microelectronic technologies have been used for fabrication of TEGs [[9], [10], [11], [12], [13], [14]]. Commercial TEGs operating at room temperature are made of telluride based materials for maximum output power 2.8 mW at 10 K temperature difference [15,16], but such materials are incompatible to CMOS or MEMS process. Silicon-germanium materials have been shown to have better performance over silicon materials in energy harvesting and they can be integrated with CMOS process as well. Their thermoelectric conversion efficiency, however, remain low at room temperature. The main problem is due to their high thermal conductivity and low figure-of-merit. Improving conversion efficiency is therefore critical so as to compete with telluride based TEGs when operating at room temperature [17]. Materials in quantum well structures with higher thermoelectric figure-of-merit have been reported two decades ago [18]. Yet it took more than another decade to see the implementation in TEG designs, where polysilicon-germanium (poly-SiGe) thin film layers in low dimensional form was shown to achieve better thermoelectric properties [19]. The poly-SiGe thin film in BiCMOS process may provide a new degree-of-freedom to increase thermoelectric conversion efficiency by tuning its Seebeck coefficient, electrical, and thermal conductivity. This paper is to extend these development such that the TEG designs by BiCMOS process in semiconductor technology can achieve higher performance for engineering applications.