Scalable and energy efficient wireless inter chip interconnection fabrics using THz-band antennas

Abstract

Computing platforms ranging from embedded systems to server blades comprise of multiple Systems-on-Chips (SoCs). Conventionally, communication between chips in these multichip platforms are realized using high-speed I/O modules over metal traces on a substrate. Due to the high-power consumption of I/O modules and non-scalable pitch of pins or solder bumps their bandwidth density and power consumption becomes bottleneck for multichip systems. Wireless chip-to-chip communication is emerging as an alternative solution to the traditional interconnection challenges of multichip systems. Novel devices based on graphene structures capable of establishing wireless links are explored in recent literature to provide high bandwidth THz links. In this work, we propose to utilize graphene-based wireless links to enable energy-efficient, multi-modal chip-to-chip communication protocol to create toroidal folding based interconnection architectures for multichip systems. With cycle-accurate simulations we demonstrate that such designs can outperform state-of-the-art wireline multichip systems.

Introduction

Platform based computing systems consisting of multiple System-on-Chips (SoCs) or multicore processors are needed to support the complexity of modern server or embedded systems. With the increase in computational demands, the number of SoCs or multicore chips in a platform have increased making the modern computing systems more complex [1]. This makes the interconnection fabric in these systems grow in both size and complexity. Therefore, the overall performance of the system depends on the efficiency of the interconnect architectures of both inter-chip and intra-chip chip communications. The advancement in intra-chip communication has been able to address the scalability and bandwidth issues by making a transition from bus-based systems to Network-on-Chip (NoC) architectures [2]. However, the performance of inter-chip communication is limited by the traditional interconnect architectures. Traditional inter-chip interconnections are realized using solder bumps or C4 interconnects placing individual chips on a substrate or Printed Circuit Board (PCB). Peripheral Component Interconnect (PCI) is one of the most common standard local I/O bus technology to interconnect board-level multichip systems. Recently, PCI express (PCIe) is presented as next generation I/O technology [3]. However, recent trends according to the International Technology Roadmap for Semiconductors (ITRS) predict that the pitch of the I/O interconnects in ICs is not scaling as fast as the gate lengths or pitch of on-chip interconnects [4], [5]. This implies a gap in density and performance of traditional I/O systems relative to on-chip interconnections. Moreover, longer and bulkier substrate traces for inter-chip communication due to the wiring complexity further aggravates the crosstalk and the signal integrity issues. Typically, inter-chip communication involves multihop paths over intra-chip global wires in both source and destination chips, I/O blocks and substrate traces. Often the intra and inter-chip communication protocols are also different to offer design flexibility but results in loss of speed and energy efficiency.

While metallic inter-chip interconnects are not scaling well, research in recent years have bought to light many alternative interconnect solutions like inter-chip photonics [6], vertically integrated monolithic 3D ICs [7] or silicon interposers [8] inductive and capacitive coupling [9] and inter-chip wireless interconnects [10], [11] as solutions to the off-chip interconnection challenges. Recent research envisions wireless communication in the Terahertz band (0.1–10 THz) as a key technology to satisfy the increasing demand for high speed communication [12]. Wireless data communication links up to several centimetres in length with graphene-based antenna arrays are demonstrated [12]. Novel transmitting and receiving devices based on micro-scale graphene structures have been investigated in [12]. These wireless interconnections are shown to improve energy efficiency and bandwidth of on-chip data communication in multicore chips over state-of-the-art counterparts [13]. While many conventional architectures have been proposed in recent time. Our study of antenna array architecture that leverages the properties of graphene-based plasmonic devices is based on [14].

In this work, we propose to use such graphene-based THz band wireless interconnects to establish a seamless communication backbone which enables data exchange between cores in a single chip as well as in a multichip system. THz band interconnects can support wider bandwidths and higher data rates compared to other wireless interconnects in Ultra-Wide Band (UWB) or millimetre wave (mm-wave) interconnects [12]. Moreover, smaller antenna sizes compared to mm-wave antennas can enable on-chip implementations of antenna arrays providing beam-steering capability. Such beam-steering will in turn support novel architectures. We propose and evaluate two interconnection architectures for multi-chip system with several multi-core processors, based on network folding approach with graphene antennas. We propose a novel multi-modal medium access mechanism to establish the wireless links between the communicating cores in the multicore system. The same switching protocol for both on-chip and inter-chip data communication is used for seamless data exchange. We perform thorough performance evaluation of the interconnection fabric based on system-level simulations and compare the proposed architectures with multiple wired traditional fabrics based on mesh or concentrated mesh topologies. We show that the use of graphene based folded architectures can reduce the energy consumption of data transfer over multichip systems compared to wireline counterpart. Finally, we also compare the graphene-based interconnection fabric with other emerging technologies like inter-chip photonic links and millimetre-wave wireless interconnects.

The rest of the paper is organized as follows. In Section 2 we summarize the related works from the focused perspective of research in wireless inter-chip interconnection fabrics and advances in graphene based on-chip THz links. In Section 3 we present the two-proposed folded graphene based wireless multi-chip interconnections and the rationale behind them. In Section 4 we present thorough performance evaluations and comparison with other architectures and technologies with conclusions in Section 5.