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An FPGA-based design for a real-time image denoising using approximated fractional integrator

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Abstract

Digital images are affected by various types of noises, which may be incorporated into the image during its acquisition, transmission etc. Removal of these unwanted noises is an essential task, especially for digital images being used for various science, engineering, and biomedical applications. Depending upon the image acquisition process/devices, transmission medium, and other factors, noise present in digital images can be modeled into various types such as Gaussian noise, salt and paper noise etc. Most of the de-noising algorithms such as bilateral filter, Gaussian filter etc., perform well for Gaussian noise. However, these algorithms perform unsatisfactorily for impulsive noise, such as speckle noise. Aim of the proposed (research) work is to develop a de-noising algorithm which can remove different types of noises especially impulsive noises from digital images with high accuracy and at the same time preserving essential or vital image information such as edges, texture information etc. Here, in this paper, we propose an image de-noising algorithm based on an approximated fractional integrator (AFI), which overcomes the above-discussed issues efficiently. It has been employed for both black & white and grayscale images. For grayscale image (because of many intensity levels), we propose a new adaptive method for selection of fractional order (q) that depends on specific features such as gradient, entropy, local roughness, and contrast of the image. A hardware implementation of the proposed algorithm using NEXYS 4 DDR Artix-7, which is a low power FPGA device is done to further validate the performance of the proposed AFI based algorithm in a practical environment. Power consumption and resource utilization of the proposed algorithm is also addressed. Finally, three different quantitative parameters i.e., peak-signal-to-noise-ratio, structural similarity index and cross-correlation has been calculated, and the proposed method is compared with some state-of-the-art techniques, which validates the effectiveness of proposed algorithm especially if impulsive noise is present in digital images.

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Acknowledgements

This publication is an outcome of the R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation (Formerly Media Lab Asia) (Grant No. U72900MH2001NPL133410).

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  1. SIPL, Department of Electrical Engineering, Indian Institute of Technology Patna, Bihta, 801103, India

    Sumit Kumar & Rajib Kumar Jha

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Kumar, S., Jha, R.K. An FPGA-based design for a real-time image denoising using approximated fractional integrator. Multidim Syst Sign Process 31, 1317–1339 (2020). https://doi.org/10.1007/s11045-020-00709-0

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