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DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems

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Abstract

Mixed-criticality systems are promoted in industry due to their potential to reduce size, weight, power, and cost. Nonetheless, deploying mixed-criticality applications on commercial multi-core platforms remains a highly challenging problem. To name a few reasons: (i) Industrial mixed-criticality applications are usually complex reactive applications, which cannot be specified by traditional, e.g., dataflow-based, models of computation. Appropriate mixed-criticality models of computation built upon Vestal’s assumptions are missing; (ii) Scheduling such applications on multicores with shared resources, such as memory buses, requires that any timing interference among applications of different criticality is bounded in order to guarantee—the necessary for certification—temporal isolation and to enable incremental design; (iii) The implementation of isolation-preserving mixed-criticality schedulers is itself subject to certification. Hence, it needs to be not only efficient, but also provably correct. This paper proposes, for the first time, a complete design flow covering all aspects from specification, using a novel mixed-criticality aware model of computation (DOL-Critical), to correct-by-construction implementation, using the principle ‘what you verify is what you generate’ which is based on a novel variant of task automata. We demonstrate the applicability of our design flow with an industrial avionic test case on the state-of-the-art Kalray MPPA®-256.

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Notes

  1. These models are used in our tool-chain for timing analysis (Sect. 4.2). The concrete class of applications and targets architectures that can be specified in DOL-Critical is described in Sect. 5.

  2. Conventional sporadic tasks assume \(a_i=1\).

  3. RTE specifies a shared resource, as described in Sect. 8.3.

  4. In reality, the blackboard is defined and implemented as a more complex object [17], for which the given simplified definition provides a reasonable abstraction.

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Acknowledgements

The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement number 288175 (CERTAINTY project).

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Authors and Affiliations

  1. Computer Engineering and Communication Networks Laboratory, ETH Zurich, 8092, Zurich, Switzerland

    Georgia Giannopoulou, Pengcheng Huang, Nikolay Stoimenov & Lothar Thiele

  2. CNRS, VERIMAG, Univ. Grenoble-Alpes, 38000, Grenoble, France

    Marius Bozga & Saddek Bensalem

  3. THALES Research and Technology, 91767, Palaiseau Cedex, France

    Sylvain Girbal, Madeleine Faugere & Romain Soulat

  4. Kalray S.A., 38330, Montbonnot Saint Martin, France

    Benoît Dupont de Dinechin

  5. Mentor, A Siemens Business, F-38334 Inovallee, Montbonnot, France

    Peter Poplavko & Dario Socci

  6. WINGS ICT Solutions PC, 189 Syggrou Avenue, 17121, Athens, Greece

    Paraskevas Bourgos

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  1. Georgia Giannopoulou
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  2. Peter Poplavko
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Correspondence to Georgia Giannopoulou.

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Peter Poplavko, Dario Socci and Paraskevas Bourgos—Ex-employees of VERIMAG (“The presented research was performed while working at VERIMAG”).

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Giannopoulou, G., Poplavko, P., Socci, D. et al. DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems. Des Autom Embed Syst 22, 141–181 (2018). https://doi.org/10.1007/s10617-018-9206-3

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