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Optimizing Sparse Matrix–Vector Multiplications on an ARMv8-based Many-Core Architecture

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Abstract

Sparse matrix–vector multiplications (SpMV) are common in scientific and HPC applications but are hard to be optimized. While the ARMv8-based processor IP is emerging as an alternative to the traditional x64 HPC processor design, there is little study on SpMV performance on such new many-cores. To design efficient HPC software and hardware, we need to understand how well SpMV performs. This work develops a quantitative approach to characterize SpMV performance on a recent ARMv8-based many-core architecture, Phytium FT-2000 Plus (FTP). We perform extensive experiments involved over 9500 distinct profiling runs on 956 sparse datasets and five mainstream sparse matrix storage formats, and compare FTP against the Intel Knights Landing many-core. We experimentally show that picking the optimal sparse matrix storage format and parameters is non-trivial as the correct decision requires expert knowledge of the input matrix and the hardware. We address the problem by proposing a machine learning based model that predicts the best storage format and parameters using input matrix features. The model automatically specializes to the many-core architectures we considered. The experimental results show that our approach achieves on average 93% of the best-available performance without incurring runtime profiling overhead.

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Notes

  1. A SpMV operation – \(\mathbf {y}=\mathbf {Ax}\) – multiplies a sparse matrix \(\mathbf {A}\) of size \(m \times n\) by a dense vector \(\mathbf {x}\) of size n, and then produces a dense vector \(\mathbf {y}\) of size m.

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Acknowledgements

This work was partially funded by the National Key R&D Program of China under Grant No. 2017YFB0202003, the National Natural Science Foundation of China under grant Agreements 61602501, 11502296, 61772542, 61561146395 and 61872294; the Open Research Program of China State Key Laboratory of Aerodynamics under grant agreement SKLA20160104; the UK Engineering and Physical Sciences Research Council under Grants EP/M01567X/1 (SANDeRs) and EP/M015793/1 (DIVIDEND); and the Royal Society International Collaboration Grant (IE161012).

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Authors and Affiliations

  1. College of Computer Science, National University of Defense Technology, Changsha, 410073, China

    Donglin Chen, Jianbin Fang, Shizhao Chen & Chuanfu Xu

  2. School of Computing and Communications, Lancaster University, Lancaster, LA1 4WA, UK

    Zheng Wang

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  1. Donglin Chen
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  2. Jianbin Fang
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Correspondence to Jianbin Fang.

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Chen, D., Fang, J., Chen, S. et al. Optimizing Sparse Matrix–Vector Multiplications on an ARMv8-based Many-Core Architecture. Int J Parallel Prog 47, 418–432 (2019). https://doi.org/10.1007/s10766-018-00625-8

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