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Analysis of preemption costs for the stack cache

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Abstract

The design of tailored hardware has proven a successful strategy to reduce the timing analysis overhead for (hard) real-time systems. The stack cache is an example of such a design that was shown to provide good average-case performance, while remaining easy to analyze. So far, however, the analysis of the stack cache was limited to individual tasks, ignoring aspects related to multitasking. A major drawback of the original stack cache design is that, due to its simplicity, it cannot hold the data of multiple tasks at the same time. Consequently, the entire cache content needs to be saved and restored when a task is preempted. We propose (a) an analysis exploiting the simplicity of the stack cache to bound the overhead induced by task preemption, (b) preemption mechanisms for the stack cache exploiting the previous analysis and, finally, (c) an extension of the design that allows to (partially) hide the overhead by virtualizing stack caches.

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Notes

  1. We assume that the stack grows towards lower addresses.

  2. This applies to the restricted placement from above as well as well-formed programs.

  3. http://www.llvm.org/.

References

  • Abbaspour S, Brandner F (2014) Alignment of memory transfers of a time-predictable stack cache. In: Proceedings of the junior researcher workshop on real-time computing

  • Abbaspour S, Brandner F, Schoeberl M (2013) A time-predictable stack cache. In: Proceedings of the workshop on software technologies for embedded and ubiquitous systems

  • Abbaspour S, Jordan A, Brandner F (2014) Lazy spilling for a time-predictable stack cache: Implementation and analysis. In: Proceedings of the workshop on worst-case execution time analysis, OASICS vol 39. pp 83–92

  • Abbaspour S, Brandner F, Naji A, Jan M (2015) Efficient context switching for the stack cache: implementation and analysis. In: Proceedings of the international conference on real time and networks systems, ACM, RTNS ’vol 15, pp 119–128

  • Aho AV, Lam MS, Sethi R, Ullman JD (2006) Compilers: principles, techniques, and tools, 2nd edn. Addison-Wesley, Boston

    MATH  Google Scholar 

  • Altmeyer S, Burguiere C (2009) A new notion of useful cache block to improve the bounds of cache-related preemption delay. In: Euromicro conference on real-time systems, ECRTS vol 09, pp 109–118

  • Altmeyer S, Davis R, Maiza C (2012) Improved cache related pre-emption delay aware response time analysis for fixed priority pre emptive systems. Real-Time Syst 48(5):499–526

    Article  MATH  Google Scholar 

  • Baruah S (2005) The limited-preemption uniprocessor scheduling of sporadic task systems. In: 17th euromicro conference on real-time systems (ECRTS’05), pp 137–144

  • Burns A (1995) Advances in real-time systems. In: preemptive priority-based scheduling: an appropriate engineering approach, Prentice-Hall, Inc., Upper Saddle River, pp 225–248

  • Chabrol D, Roux D, David V, Jan M, Hmid MA, Oudin P, Zeppa G (2013) Time- and angle-triggered real-time kernel. In: Design, automation and test in Europe, DATE vol 13, pp 1060–1062

  • Cormen TH, Leiserson CE, Rivest RL, Stein C (2009) Introduction to algorithms, 3rd edn. MIT Press, Cambridge

    MATH  Google Scholar 

  • Guthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB (2001) MiBench: a free, commercially representative embedded benchmark suite. In: Proceedings of the workshop on workload characterization, WWC ’01

  • Hecht MS, Ullman JD (1973) Analysis of a simple algorithm for global data flow problems. In: Symposium on principles of programming languages (POPL’73), ACM, pp 207–217

  • Jan M, David V, Lalande J, Pitel M (2010) Usage of the safety-oriented real-time oasis approach to build deterministic protection relays. In: Symposium on industrial embedded systems, SIES’10, pp 128–135

  • Jordan A, Brandner F, Schoeberl M (2013) Static analysis of worst-case stack cache behavior. In: Proceedings of the conference on real-time networks and systems, RTNS’13, pp 55–64

  • Kam JB, Ullman JD (1976) Global data flow analysis and iterative algorithms. J ACM 23(1):158–171

    Article  MathSciNet  MATH  Google Scholar 

  • Lee CG, Hahn J, Seo YM, Min SL, Ha R, Hong S, Park CY, Lee M, Kim CS (1998) Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans Comput 47(6):700–713

    Article  MathSciNet  Google Scholar 

  • Li YTS, Malik S (1995) Performance analysis of embedded software using implicit path enumeration. In: Proceedings of the design automation conference, ACM, DAC ’95, pp 456–461

  • Metzlaff S, Guliashvili I, Uhrig S, Ungerer T (2011) A dynamic instruction scratchpad memory for embedded processors managed by hardware. In: Proceedings of the architecture of computing systems conference, Springer, pp 122–134

  • Mische J, Uhrig S, Kluge F, Ungerer T (2010) Using smt to hide context switch times of large real-time tasksets. In: Proceedings of conference on embedded and real-time computing systems and applications, RTCSA’10, pp 255–264

  • Olson LE, Eckert Y, Manne S, Hill MD (2014) Revisiting stack caches for energy efficiency. Tech. Rep. TR1813, University of Wisconsin

  • Reineke J, Liu I, Patel HD, Kim S, Lee EA (2011) PRET DRAM controller: bank privatization for predictability and temporal isolation. In: Proceedings of the conference on hardware/software codesign and system synthesis, pp 99–108

  • Rochange C, Uhrig S, Sainrat P (2014) Time-predictable architectures. ISTE Wiley, London

    Google Scholar 

  • Schoeberl M, Schleuniger P, Puffitsch W, Brandner F, Probst C, Karlsson S, Thorn T (2011) Towards a time-predictable dual-issue microprocessor: the patmos approach. In: Proceedings of bringing theory to practice: predictability and performance in embedded systems, OASICS, vol 18, pp 11–21

  • Soundararajan V, Agarwal A (1992) Dribbling registers: a mechanism for reducing context switch latency in large-scale multiprocessors. Tech. rep

  • Thorup M (2004) Integer priority queues with decrease key in constant time and the single source shortest paths problem. J Comput Syst Sci 69(3):330–353

    Article  MathSciNet  MATH  Google Scholar 

  • Tune E, Kumar R, Tullsen DM, Calder B (2004) Balanced multithreading: Increasing throughput via a low cost multithreading hierarchy. In: Proceedings of the symposium on microarchitecture, MICRO’04, pp 183–194

  • Wang Y, Saksena M (1999) Scheduling fixed-priority tasks with preemption threshold. In: Real-time computing systems and applications, 1999. RTCSA ’99. sixth international conference on, pp 328–335

  • Wilhelm R, Grund D, Reineke J, Schlickling M, Pister M, Ferdinand C (2009) Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. Trans Comput-Aided Des Integr Circ Syst 28(7):966–978

    Article  Google Scholar 

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Acknowledgements

This work was supported by a Grant (2014-0741D) from Digiteo France: “Profiling Metrics and Techniques for the Optimization of Real-Time Programs” (PM-TOP).

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Authors and Affiliations

  1. U2IS, ENSTA ParisTech, Université Paris-Saclay, Palaiseau Cedex, France

    Amine Naji

  2. Department of Applied Mathematics and Computer Science, Technical University of Denmark, Lyngby, Denmark

    Sahar Abbaspour

  3. LTCI, Télécom ParisTech, Université Paris-Saclay, Paris, France

    Florian Brandner

  4. Embedded Real Time Systems Laboratory, CEA, LIST, Saclay, France

    Mathieu Jan

Authors
  1. Amine Naji
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  2. Sahar Abbaspour
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  3. Florian Brandner
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  4. Mathieu Jan
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Corresponding author

Correspondence to Amine Naji.

Additional information

This work is an extension of the paper “Efficient Context Switching for the Stack Cache: Implementation and Analysis” by Abbaspour et al. (2015). It was partially supported by a Grant (2014-0741D) from Digiteo France: “Profiling Metrics and Techniques for the Optimization of Real-Time Programs” (PM-TOP).

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Naji, A., Abbaspour, S., Brandner, F. et al. Analysis of preemption costs for the stack cache. Real-Time Syst 54, 700–744 (2018). https://doi.org/10.1007/s11241-018-9298-7

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