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TTHLS: an HLS tool for testable hardware generation

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Abstract

This paper presents a new methodology to incorporate testability to Technology driven high-level synthesis, which is a customized high level synthesis approach based on the target technology. This new methodology called testable technology driven high-level synthesis, generates testable hardware from the corresponding HDL input. Testability incorporation at this higher abstraction, using this integrated approach, proves to be better in terms of area and power consumption than the conventional approaches. The experimental results for the examples considered here prove that the proposed method can reduce up to 9.38% in terms of silicon area and 1.89% in terms of power consumption.

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Acknowledgements

We thank the anonymous reviewers for having given most valuable suggestions for the improvement of this paper.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, The Kavery Engineering College, Salem, Tamilnadu, India

    S. Ravi

  2. Department of Computer Science and Engineering, St. Joseph’s College of Engineering and Technology, Thanjavur, Tamilnadu, India

    M. Joseph

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  1. S. Ravi
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  2. M. Joseph
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Correspondence to S. Ravi.

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Ravi, S., Joseph, M. TTHLS: an HLS tool for testable hardware generation. Des Autom Embed Syst 21, 231–246 (2017). https://doi.org/10.1007/s10617-017-9192-x

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  • DOI: https://doi.org/10.1007/s10617-017-9192-x

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